| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_lvds.c | 326 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000))
340 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000))
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| intel_dp.c | 943 return I915_READ(PP_STATUS(pipe)) & PP_ON;
1056 i915_reg_t pp_on; member in struct:pps_registers
1076 regs->pp_on = PP_ON_DELAYS(pps_idx);
1150 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
2595 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2596 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2598 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2601 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
6727 u32 pp_on, pp_off, pp_ctl; local in function:intel_pps_readout_hw_state
6738 pp_on = I915_READ(regs.pp_on)
6879 u32 pp_on, pp_off, port_sel = 0; local in function:intel_dp_init_panel_power_sequencer_registers
[all...] |
| intel_display_power.c | 4530 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON,
|
| /src/sys/external/bsd/drm/dist/shared-core/ |
| i915_reg.h | 716 #define PP_ON (1 << 31)
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| handlers.c | 383 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
390 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_reg.h | 4859 #define PP_ON REG_BIT(31)
|
