| /src/external/gpl3/binutils/dist/include/opcode/ |
| v850.h | 84 #define PROCESSOR_V850E2_UP (PROCESSOR_V850E2 | PROCESSOR_V850E2V3_UP)
85 #define PROCESSOR_V850E_UP (PROCESSOR_V850E | PROCESSOR_V850E1 | PROCESSOR_V850E2_UP)
|
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| v850.h | 84 #define PROCESSOR_V850E2_UP (PROCESSOR_V850E2 | PROCESSOR_V850E2V3_UP)
85 #define PROCESSOR_V850E_UP (PROCESSOR_V850E | PROCESSOR_V850E1 | PROCESSOR_V850E2_UP)
|
| /src/external/gpl3/gdb/dist/include/opcode/ |
| v850.h | 84 #define PROCESSOR_V850E2_UP (PROCESSOR_V850E2 | PROCESSOR_V850E2V3_UP)
85 #define PROCESSOR_V850E_UP (PROCESSOR_V850E | PROCESSOR_V850E1 | PROCESSOR_V850E2_UP)
|
| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| v850.h | 84 #define PROCESSOR_V850E2_UP (PROCESSOR_V850E2 | PROCESSOR_V850E2V3_UP)
85 #define PROCESSOR_V850E_UP (PROCESSOR_V850E | PROCESSOR_V850E1 | PROCESSOR_V850E2_UP)
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| v850-opc.c | 1344 { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1449 { "caxi", two (0x07e0, 0x00ee), two (0x07e0, 0x07ff), {R1, R2, R3}, 1, PROCESSOR_V850E2_UP },
1491 { "divq", two (0x07e0, 0x02fc), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1493 { "divqu", two (0x07e0, 0x02fe), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1503 { "eiret", two (0x07e0, 0x0148), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP },
1507 { "feret", two (0x07e0, 0x014a), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP },
1509 { "fetrap", one (0x0040), one (0x87ff), {I4U_NOTIMM0}, 0, PROCESSOR_V850E2_UP },
1513 { "hsh", two (0x07e0, 0x0346), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1522 { "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP },
1528 { "jarl32", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }
[all...] |
| v850-dis.c | 703 && ((target_processor & PROCESSOR_V850E2_UP) != 0))
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| v850-opc.c | 1344 { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1449 { "caxi", two (0x07e0, 0x00ee), two (0x07e0, 0x07ff), {R1, R2, R3}, 1, PROCESSOR_V850E2_UP },
1491 { "divq", two (0x07e0, 0x02fc), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1493 { "divqu", two (0x07e0, 0x02fe), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1503 { "eiret", two (0x07e0, 0x0148), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP },
1507 { "feret", two (0x07e0, 0x014a), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP },
1509 { "fetrap", one (0x0040), one (0x87ff), {I4U_NOTIMM0}, 0, PROCESSOR_V850E2_UP },
1513 { "hsh", two (0x07e0, 0x0346), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1522 { "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP },
1528 { "jarl32", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }
[all...] |
| v850-dis.c | 703 && ((target_processor & PROCESSOR_V850E2_UP) != 0))
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| v850-opc.c | 1344 { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1449 { "caxi", two (0x07e0, 0x00ee), two (0x07e0, 0x07ff), {R1, R2, R3}, 1, PROCESSOR_V850E2_UP },
1491 { "divq", two (0x07e0, 0x02fc), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1493 { "divqu", two (0x07e0, 0x02fe), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1503 { "eiret", two (0x07e0, 0x0148), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP },
1507 { "feret", two (0x07e0, 0x014a), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP },
1509 { "fetrap", one (0x0040), one (0x87ff), {I4U_NOTIMM0}, 0, PROCESSOR_V850E2_UP },
1513 { "hsh", two (0x07e0, 0x0346), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1522 { "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP },
1528 { "jarl32", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }
[all...] |
| v850-dis.c | 703 && ((target_processor & PROCESSOR_V850E2_UP) != 0))
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| v850-opc.c | 1344 { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1449 { "caxi", two (0x07e0, 0x00ee), two (0x07e0, 0x07ff), {R1, R2, R3}, 1, PROCESSOR_V850E2_UP },
1491 { "divq", two (0x07e0, 0x02fc), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1493 { "divqu", two (0x07e0, 0x02fe), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1503 { "eiret", two (0x07e0, 0x0148), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP },
1507 { "feret", two (0x07e0, 0x014a), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP },
1509 { "fetrap", one (0x0040), one (0x87ff), {I4U_NOTIMM0}, 0, PROCESSOR_V850E2_UP },
1513 { "hsh", two (0x07e0, 0x0346), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1522 { "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP },
1528 { "jarl32", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }
[all...] |
| v850-dis.c | 703 && ((target_processor & PROCESSOR_V850E2_UP) != 0))
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-v850.c | 650 { "bsel", 31, PROCESSOR_V850E2_UP },
655 { "dbic", 15, PROCESSOR_V850E2_UP },
658 { "dbwr", 30, PROCESSOR_V850E2_UP },
676 { "eiic", 13, PROCESSOR_V850E2_UP },
679 { "eiwr", 28, PROCESSOR_V850E2_UP },
680 { "feic", 14, PROCESSOR_V850E2_UP },
683 { "fewr", 29, PROCESSOR_V850E2_UP },
3061 if ((processor_mask & PROCESSOR_V850E2_UP) == 0 || default_disp_size == 22)
3083 || (processor_mask & PROCESSOR_V850E2_UP) == 0)
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-v850.c | 655 { "bsel", 31, PROCESSOR_V850E2_UP },
660 { "dbic", 15, PROCESSOR_V850E2_UP },
663 { "dbwr", 30, PROCESSOR_V850E2_UP },
681 { "eiic", 13, PROCESSOR_V850E2_UP },
684 { "eiwr", 28, PROCESSOR_V850E2_UP },
685 { "feic", 14, PROCESSOR_V850E2_UP },
688 { "fewr", 29, PROCESSOR_V850E2_UP },
3066 if ((processor_mask & PROCESSOR_V850E2_UP) == 0 || default_disp_size == 22)
3088 || (processor_mask & PROCESSOR_V850E2_UP) == 0)
|
