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      1 /*	$NetBSD: mpc5200_ac97reg.h,v 1.1 2026/06/27 13:28:35 rkujawa Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2026 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Radoslaw Kujawa.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _POWERPC_MPC5200_AC97REG_H_
     33 #define _POWERPC_MPC5200_AC97REG_H_
     34 
     35 /*
     36  * PSC AC97-mode register additions.
     37  */
     38 
     39 /* AC97-mode register offsets not present in pscreg.h. */
     40 #define	PSC_AC97SLOTS	0x24	/* AC97 Slots Register (wo, 32-bit)	*/
     41 #define	PSC_AC97CMD	0x28	/* AC97 Command Register (rw, 32-bit)	*/
     42 #define	PSC_AC97DATA	0x2c	/* AC97 Status Data Register (ro, 32-bit) */
     43 #define	PSC_OP1		0x38	/* Output Port 1 Bit Set (wo, 8-bit)	*/
     44 #define	PSC_OP0		0x3c	/* Output Port 0 Bit Set (wo, 8-bit)	*/
     45 #define	PSC_RFCNTL	0x68	/* Rx FIFO Control (8-bit)		*/
     46 #define	PSC_RFALARM	0x6e	/* Rx FIFO Alarm threshold (16-bit)	*/
     47 #define	PSC_TFCNTL	0x88	/* Tx FIFO Control (8-bit)		*/
     48 #define	PSC_TFALARM	0x8e	/* Tx FIFO Alarm threshold (16-bit)	*/
     49 
     50 /*
     51  * Serial Interface Control Register (PSC_SICR, 0x40) bits for AC97 mode
     52  */
     53 #define	SICR_SIM_AC97		0x03000000	/* SIM = 0b0011 (AC97)	*/
     54 #define	SICR_ENAC97		0x00010000	/* normal (enhanced) AC97 */
     55 #define	SICR_NORMAL_AC97	(SICR_SIM_AC97 | SICR_ENAC97)
     56 
     57 /*
     58  * AC97 Slots Register (PSC_AC97SLOTS, 0x24)
     59  */
     60 #define	AC97SLOTS_TX_SLOT(n)	(1u << (28 - (n)))	/* n = 3..12 */
     61 #define	AC97SLOTS_RX_SLOT(n)	(1u << (15 - (n)))	/* n = 3..12 */
     62 #define	AC97SLOTS_TX_STEREO	(AC97SLOTS_TX_SLOT(3) | AC97SLOTS_TX_SLOT(4))
     63 #define	AC97SLOTS_RX_STEREO	(AC97SLOTS_RX_SLOT(3) | AC97SLOTS_RX_SLOT(4))
     64 
     65 /*
     66  * AC97 Command Register (PSC_AC97CMD, 0x28)
     67  */
     68 #define	AC97CMD_READ		0x80000000	/* bit 0: 1 = read	*/
     69 #define	AC97CMD_INDEX(reg)	((uint32_t)((reg) & 0x7f) << 24)
     70 #define	AC97CMD_DATA(val)	((uint32_t)((val) & 0xffff) << 8)
     71 #define	AC97CMD_WRITE(reg, val)	(AC97CMD_INDEX(reg) | AC97CMD_DATA(val))
     72 
     73 /*
     74  * AC97 Status Data Register (PSC_AC97DATA, 0x2c)
     75  */
     76 #define	AC97DATA_VALUE(d)	(((d) >> 8) & 0xffff)
     77 
     78 /*
     79  * Status Register (PSC_SR, 0x04)
     80  */
     81 #define	AC97_SR_CMD_SEND	0x0008	/* AC97CMD written, not yet sent	*/
     82 #define	AC97_SR_DATA_OVR	0x0004	/* read response overran	*/
     83 #define	AC97_SR_DATA_VALID	0x0002	/* read response available	*/
     84 #define	AC97_SR_UNEX_RX_SLOT	0x0001	/* unexpected receive slots	*/
     85 
     86 /*
     87  * Output Port bit for the codec RES line
     88  */
     89 #define	AC97_OP_RES		0x02
     90 
     91 #endif /* _POWERPC_MPC5200_AC97REG_H_ */
     92