HomeSort by: relevance | last modified time | path
    Searched refs:PWR (Results 1 - 9 of 9) sorted by relevancy

  /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.base/
sigall.exp 44 # the raised signal as PWR.
46 set esig "PWR"
117 PWR
  /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.base/
sigall.exp 44 # the raised signal as PWR.
46 set esig "PWR"
117 PWR
  /src/sys/dev/i2c/
mt2131.c 42 #define PWR 0x07
211 ret = mt2131_write(sc, PWR, 0xf2);
  /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.reverse/
sigall-reverse.exp 185 PWR
sigall-precsave.exp 189 PWR
  /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.reverse/
sigall-reverse.exp 185 PWR
sigall-precsave.exp 189 PWR
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu10_hwmgr.c 321 reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_0.c 2736 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
2741 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2747 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2752 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);

Completed in 54 milliseconds