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    Searched refs:PhiReg (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MVETPAndVPTOptimisationsPass.cpp 348 Register PhiReg = LoopPhi->getOperand(0).getReg();
374 if (!CheckUsers(PhiReg, {LoopDec}, MRI) ||
388 MRI->constrainRegClass(PhiReg, &ARM::GPRlrRegClass);
403 .addReg(PhiReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonHardwareLoops.cpp 1636 Register PhiReg = Phi->getOperand(i).getReg();
1637 MachineInstr *DI = MRI->getVRegDef(PhiReg);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ModuloSchedule.cpp 1662 Register PhiReg = MI.getOperand(0).getReg();
1665 MI.getOperand(0).setReg(PhiReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 3496 unsigned InitReg, unsigned ResultReg, unsigned PhiReg,
3511 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
3586 unsigned InitResultReg, unsigned PhiReg, int Offset,
3615 InitResultReg, DstReg, PhiReg, TmpExec,
3743 Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3749 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset,
3848 Register PhiReg = MRI.createVirtualRegister(VecRC);
3851 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, Offset,
3860 .addReg(PhiReg)
3868 .addReg(PhiReg)
    [all...]
AMDGPURegisterBankInfo.cpp 745 Register PhiReg = MRI.createGenericVirtualRegister(ResTy);
747 PhiRegs.push_back(PhiReg);
748 MRI.setRegBank(PhiReg, *DefBank);

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