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    Searched refs:PredOp (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonExpandCondsets.cpp 217 unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
228 const MachineOperand &PredOp, bool Cond,
622 /// PredOp. The Cond argument specifies whether the predicate is to be
623 /// if(PredOp), or if(!PredOp).
626 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp,
640 unsigned PredState = getRegState(PredOp) & ~RegState::Kill;
649 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
654 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()
    [all...]
HexagonGenMux.cpp 245 MachineOperand &PredOp = MI->getOperand(1);
246 if (PredOp.isUndef())
249 Register PR = PredOp.getReg();
HexagonISelLowering.cpp 1092 SDValue PredOp = Op.getOperand(0);
1104 DAG.getSelect(dl, WideTy, PredOp,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CombinerHelper.cpp 3205 MachineOperand &PredOp = Def->getOperand(1);
3207 (CmpInst::Predicate)PredOp.getPredicate());
3208 PredOp.setPredicate(NewP);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 1572 auto PredOp = ICmp.getOperand(1);
1573 emitIntegerCompare(ICmp.getOperand(2), ICmp.getOperand(3), PredOp, MIB);
1575 static_cast<CmpInst::Predicate>(PredOp.getPredicate()));

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