| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.h | 78 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
84 Register &PredReg);
86 Register PredReg;
87 return getVPTInstrPredicate(MI, PredReg);
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| ARMLoadStoreOptimizer.cpp | 173 ARMCC::CondCodes Pred, unsigned PredReg);
177 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
183 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
488 unsigned PredReg) {
557 .addReg(PredReg);
578 .addReg(PredReg);
628 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
748 .add(predOps(Pred, PredReg));
759 .add(predOps(Pred, PredReg));
765 .add(predOps(Pred, PredReg));
[all...] |
| Thumb2InstrInfo.cpp | 73 Register PredReg;
74 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);
121 Register PredReg;
122 return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;
279 ARMCC::CondCodes Pred, Register PredReg,
285 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
302 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
309 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
318 .add(predOps(Pred, PredReg))
330 .add(predOps(Pred, PredReg))
[all...] |
| MVEVPTBlockPass.cpp | 106 Register PredReg;
110 NextPred = getVPTInstrPredicate(*Iter, PredReg);
240 Register PredReg;
243 ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*MI, PredReg);
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| ThumbRegisterInfo.h | 43 Register PredReg = Register(),
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| Thumb2SizeReduction.cpp | 471 Register PredReg = MI->getOperand(5).getReg();
484 .addReg(PredReg)
689 Register PredReg;
690 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) {
731 Register PredReg;
733 if (getInstrPredicate(*MI, PredReg) != ARMCC::AL)
802 Register PredReg;
803 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
895 Register PredReg;
896 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
[all...] |
| ThumbRegisterInfo.cpp | 65 ARMCC::CondCodes Pred, unsigned PredReg,
77 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
85 ARMCC::CondCodes Pred, unsigned PredReg,
106 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const {
113 PredReg, MIFlags);
116 PredReg, MIFlags);
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| Thumb2ITBlockPass.cpp | 202 Register PredReg;
203 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
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| MLxExpansionPass.cpp | 282 Register PredReg = MI->getOperand(++NextOp).getReg();
295 MIB.addImm(Pred).addReg(PredReg);
307 MIB.addImm(Pred).addReg(PredReg);
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| ARMBaseInstrInfo.h | 539 /// \p PredReg if that is not the case.
541 unsigned PredReg = 0) {
543 MachineOperand::CreateReg(PredReg, false)}};
767 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
783 ARMCC::CondCodes Pred, Register PredReg,
790 ARMCC::CondCodes Pred, Register PredReg,
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| ARMBaseRegisterInfo.cpp | 480 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const {
492 .add(predOps(Pred, PredReg))
829 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg();
843 Offset, Pred, PredReg, TII);
847 Offset, Pred, PredReg, TII);
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| ARMBaseRegisterInfo.h | 190 Register PredReg = Register(),
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| ARMConstantIslandPass.cpp | 1410 Register PredReg;
1413 getITInstrPredicate(*I, PredReg) != ARMCC::AL;
1456 Register PredReg;
1457 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
1480 Register PredReg;
1481 assert(!isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL);
1885 Register PredReg;
1887 ARMCC::CondCodes Pred = getInstrPredicate(*Br.MI, PredReg);
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| ARMFrameLowering.cpp | 244 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
247 Pred, PredReg, TII, MIFlags);
250 Pred, PredReg, TII, MIFlags);
258 unsigned PredReg = 0) {
260 MIFlags, Pred, PredReg);
2315 unsigned PredReg = TII.getFramePred(Old);
2318 Pred, PredReg);
2322 Pred, PredReg);
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| ARMISelDAGToDAG.cpp | 1737 SDValue PredReg;
1755 PredReg = CurDAG->getRegister(0, MVT::i32);
1771 PredReg = LD->getMask();
1816 CurDAG->getTargetConstant(Pred, SDLoc(N), MVT::i32), PredReg,
2883 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2885 Ops.push_back(PredReg);
4066 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
4067 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
4089 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
4090 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
[all...] |
| ARMBaseInstrInfo.cpp | 2221 Register &PredReg) {
2224 PredReg = 0;
2228 PredReg = MI.getOperand(PIdx+1).getReg();
2251 Register PredReg;
2252 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
2254 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
2456 ARMCC::CondCodes Pred, Register PredReg,
2462 .add(predOps(Pred, PredReg))
2486 .add(predOps(Pred, PredReg))
5499 Register PredReg;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCompound.cpp | 177 unsigned PredReg = Predicate.getReg();
179 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) ||
180 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3));
187 return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt;
189 return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t;
191 return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt;
193 return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t;
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| HexagonMCChecker.h | 81 void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue);
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| HexagonMCChecker.cpp | 66 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
70 PredReg = R;
75 NewPreds.insert(PredReg);
91 unsigned PredReg = Hexagon::NoRegister;
97 initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue);
99 initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue);
127 Defs[R].insert(PredSense(PredReg, isTrue));
182 Defs[*SRI].insert(PredSense(PredReg, isTrue));
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| HexagonMCDuplexInfo.cpp | 190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
477 PredReg = MCI.getOperand(1).getReg(); // P0
479 Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) {
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonGenPredicate.cpp | 121 bool isScalarPred(RegisterSubReg PredReg);
323 bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) {
325 WorkQ.push(PredReg);
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| HexagonInstrInfo.h | 428 bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
462 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
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| HexagonInstrInfo.cpp | 1614 unsigned PredReg, PredRegPos, PredRegFlags;
1615 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1618 T.addReg(PredReg, PredRegFlags);
1632 MRI.clearKillFlags(PredReg);
3131 unsigned PredReg) const {
3134 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3136 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
4442 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4450 PredReg = Cond[1].getReg();
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| HexagonHardwareLoops.cpp | 648 unsigned PredReg, PredPos, PredRegFlags;
649 if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags))
651 MachineInstr *CondI = MRI->getVRegDef(PredReg);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.h | 356 unsigned PredReg,
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