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    Searched refs:PredSU (Results 1 - 12 of 12) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUExportClustering.cpp 70 SUnit *PredSU = Pred.getSUnit();
71 if (!isExport(*PredSU) && !Pred.isWeak())
72 DAG->addEdge(ChainHead, SDep(PredSU, SDep::Artificial));
86 SUnit *PredSU = Pred.getSUnit();
87 if (Pred.isBarrier() && isExport(*PredSU)) {
94 for (const SDep &ExportPred : PredSU->Preds) {
GCNILPSched.cpp 66 SUnit *PredSU = Pred.getSUnit();
67 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers);
277 auto PredSU = PredEdge.getSUnit();
280 assert(PredSU->isBoundaryNode() || PredSU->NumSuccsLeft > 0);
282 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge.getLatency());
284 if (!PredSU->isBoundaryNode() && --PredSU->NumSuccsLeft == 0)
285 PendingQueue.push_front(*new (Alloc.Allocate()) Candidate(PredSU));
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGRRList.cpp 399 SUnit *PredSU = PredEdge->getSUnit();
402 if (PredSU->NumSuccsLeft == 0) {
404 dumpNode(*PredSU);
409 --PredSU->NumSuccsLeft;
414 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());
419 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
420 PredSU->isAvailable = true;
422 unsigned Height = PredSU->getHeight();
426 if (isReady(PredSU)) {
    [all...]
ResourcePriorityQueue.cpp 77 SUnit *PredSU = Pred.getSUnit();
78 const SDNode *ScegN = PredSU->getNode();
217 SUnit &PredSU = *Pred.getSUnit();
218 if (!PredSU.isScheduled) {
221 if (OnlyAvailablePred && OnlyAvailablePred != &PredSU)
223 OnlyAvailablePred = &PredSU;
ScheduleDAGFast.cpp 140 SUnit *PredSU = PredEdge->getSUnit();
143 if (PredSU->NumSuccsLeft == 0) {
145 dumpNode(*PredSU);
150 --PredSU->NumSuccsLeft;
154 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
155 PredSU->isAvailable = true;
156 AvailableQueue.push(PredSU);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ScheduleDAG.cpp 118 SUnit *PredSU = PredDep.getSUnit();
122 for (SDep &SuccDep : PredSU->Succs) {
240 SUnit *PredSU = PredDep.getSUnit();
241 if (PredSU->isHeightCurrent)
242 WorkList.push_back(PredSU);
273 SUnit *PredSU = PredDep.getSUnit();
274 if (PredSU->isDepthCurrent)
276 PredSU->Depth + PredDep.getLatency());
279 WorkList.push_back(PredSU);
ScheduleDAGInstrs.cpp 1203 bool ScheduleDAGInstrs::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
1204 return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU);
1232 /// List PredSU, SuccSU pairs that represent data edges between subtrees.
1370 const SUnit *PredSU = PredDep.getSUnit();
1371 unsigned PredNum = PredSU->NodeNum;
1378 for (const SDep &SuccDep : PredSU->Succs) {
CriticalAntiDepBreaker.cpp 146 const SUnit *PredSU = P.getSUnit();
148 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
MachineScheduler.cpp 673 /// FIXME: Adjust PredSU height based on MinLatency.
675 SUnit *PredSU = PredEdge->getSUnit();
678 --PredSU->WeakSuccsLeft;
680 NextClusterPred = PredSU;
684 if (PredSU->NumSuccsLeft == 0) {
686 dumpNode(*PredSU);
693 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency())
694 PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency();
696 --PredSU->NumSuccsLeft;
697 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU
    [all...]
AggressiveAntiDepBreaker.cpp 277 const SUnit *PredSU = Pred.getSUnit();
279 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
MachinePipeliner.cpp 2781 SUnit *PredSU = PredEdge.getSUnit();
2783 *llvm::lower_bound(Indices, std::make_pair(PredSU, 0), CompareKey));
2784 if (!PredSU->getInstr()->isPHI() && PredIndex < Index) {
2786 Pred = PredSU;
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ScheduleDAGInstrs.h 352 /// True if an edge can be added from PredSU to SuccSU without creating
354 bool canAddEdge(SUnit *SuccSU, SUnit *PredSU);

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