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    Searched refs:PrevReg (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegAllocFast.cpp 850 MCPhysReg PrevReg = LRI->PhysReg;
851 if (PrevReg != 0 && isRegUsedInInstr(PrevReg, true)) {
852 LLVM_DEBUG(dbgs() << "Need new assignment for " << printReg(PrevReg, TRI)
854 freePhysReg(PrevReg);
860 << printReg(PrevReg, TRI) << '\n');
862 TII->get(TargetOpcode::COPY), PrevReg)
ModuloSchedule.cpp 561 unsigned PrevReg = 0;
563 PrevReg = VRMap[PrevStage - np][LoopVal];
565 NewReg, PrevReg);
1143 unsigned PrevReg) {
1171 if (PrevReg && InProlog)
1172 ReplaceReg = PrevReg;
1173 else if (PrevReg && !isLoopCarried(*Phi) &&
1175 ReplaceReg = PrevReg;
RegAllocGreedy.cpp 471 Register canReassign(LiveInterval &VirtReg, Register PrevReg) const;
853 Register RAGreedy::canReassign(LiveInterval &VirtReg, Register PrevReg) const {
858 if ((*I).id() == PrevReg.id())
874 << printReg(PrevReg, TRI) << " to "
MachinePipeliner.cpp 2186 unsigned PrevReg = getLoopPhiReg(*Phi, MI->getParent());
2187 if (!PrevReg)
2191 MachineInstr *PrevDef = MRI.getVRegDef(PrevReg);
2216 NewBase = PrevReg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILowerI1Copies.cpp 88 unsigned DstReg, unsigned PrevReg, unsigned CurReg);
810 unsigned PrevReg, unsigned CurReg) {
812 bool PrevConstant = isConstantLaneMask(PrevReg, PrevVal);
833 PrevMaskedReg = PrevReg;
837 .addReg(PrevReg)
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ModuloSchedule.h 229 unsigned NewReg, unsigned PrevReg = 0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/
SparcAsmParser.cpp 588 MCOperand PrevReg = MCOperand::createReg(Sparc::G0);
601 PrevReg = MCRegOp;
624 TmpInst.addOperand(PrevReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 1422 int PrevReg = *RegList.List->begin();
1425 if ( Reg != PrevReg + 1)
1427 PrevReg = Reg;
6793 unsigned PrevReg = Mips::NoRegister;
6812 unsigned TmpReg = PrevReg + 1;
6821 PrevReg = TmpReg;
6828 if ((PrevReg == Mips::NoRegister) &&
6841 } else if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) &&
6865 PrevReg = RegNo
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 3512 int64_t PrevReg = FirstReg;
3530 unsigned Space = (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + 32 - PrevReg);
3556 (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32) {
3561 PrevReg = Reg;

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