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    Searched refs:ProcModel (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
SubtargetEmitter.cpp 95 unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
97 void EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
99 void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
103 void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
105 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
108 const CodeGenProcModel &ProcModel);
110 const CodeGenProcModel &ProcModel);
112 const CodeGenProcModel &ProcModel);
113 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
385 for (const CodeGenProcModel &ProcModel : SchedModels.procModels())
    [all...]
DFAPacketizerEmitter.cpp 219 for (const CodeGenProcModel &ProcModel : CGS.procModels()) {
220 if (ProcModel.hasItineraries()) {
221 auto NS = ProcModel.ItinsDef->getValueAsString("PacketizerNamespace");
222 ItinsByNamespace[std::string(NS)].push_back(&ProcModel);
CodeGenSchedule.cpp 794 const CodeGenProcModel &ProcModel) const {
802 if (&getProcModel(ModelDef) != &ProcModel)
807 "defined for processor " + ProcModel.ModelName +
813 RWSeq, IsRead,ProcModel);
824 expandRWSeqForProc(Idx, RWSeq, IsRead, ProcModel);
933 const CodeGenProcModel &ProcModel =
935 ProcIndices.push_back(ProcModel.Index);
936 LLVM_DEBUG(dbgs() << "InstRW on " << ProcModel.ModelName << " for "
1149 for (CodeGenProcModel &ProcModel : ProcModels) {
1150 if (!ProcModel.hasItineraries()
    [all...]
CodeGenSchedule.h 566 const CodeGenProcModel &ProcModel) const;

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