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    Searched refs:PtrReg (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCallLowering.cpp 423 Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy);
424 lowerParameterPtr(PtrReg, B, ParamTy, Offset);
432 B.buildLoad(DstReg, PtrReg, *MMO);
541 Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy);
542 lowerParameterPtr(PtrReg, B, ArgTy, ArgOffset);
544 B.buildAddrSpaceCast(VRegs[i][0], PtrReg);
AMDGPURegisterBankInfo.cpp 1165 Register PtrReg = MI.getOperand(1).getReg();
1176 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0);
1180 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0);
1184 B.buildLoadFromOffset(MI.getOperand(0), PtrReg, *MMO, 0);
1191 auto Load0 = B.buildLoadFromOffset(Part64, PtrReg, *MMO, 0);
1192 auto Load1 = B.buildLoadFromOffset(Part32, PtrReg, *MMO, 8);
1199 auto WideLoad = B.buildLoadFromOffset(WiderTy, PtrReg, *MMO, 0);
3204 Register PtrReg) const {
3205 LLT PtrTy = MRI.getType(PtrReg);
3213 const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI)
    [all...]
AMDGPULegalizerInfo.cpp 2397 Register PtrReg = MI.getOperand(1).getReg();
2398 LLT PtrTy = MRI.getType(PtrReg);
2403 auto Cast = B.buildAddrSpaceCast(ConstPtr, PtrReg);
2444 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0);
2452 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0);
2460 B.buildLoadFromOffset(WideLoad, PtrReg, *MMO, 0);
2496 Register PtrReg = MI.getOperand(1).getReg();
2500 assert(AMDGPU::isFlatGlobalAddrSpace(MRI.getType(PtrReg).getAddressSpace()) &&
2510 .addUse(PtrReg)
AMDGPUInstructionSelector.cpp 2371 Register PtrReg = MI.getOperand(1).getReg();
2372 const LLT PtrTy = MRI->getType(PtrReg);
3383 unsigned PtrReg = GEPInfo.SgprParts[0];
3385 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
3399 Register PtrReg = GEPInfo.SgprParts[0];
3406 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
3433 Register PtrReg = GEPInfo.SgprParts[0];
3438 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CombinerHelper.cpp 2314 MachineInstr &MI, std::pair<Register, bool> &PtrReg) {
2322 PtrReg.second = false;
2324 if (mi_match(SrcReg, MRI, m_GPtrToInt(m_Reg(PtrReg.first)))) {
2327 LLT PtrTy = MRI.getType(PtrReg.first);
2332 PtrReg.second = true;
2339 MachineInstr &MI, std::pair<Register, bool> &PtrReg) {
2344 const bool DoCommute = PtrReg.second;
2347 LHS = PtrReg.first;
LegalizerHelper.cpp 917 Register PtrReg = MI.getOperand(1).getReg();
924 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
926 MIRBuilder.buildLoadInstr(MI.getOpcode(), TmpReg, PtrReg, MMO);
2721 Register PtrReg = MI.getOperand(1).getReg();
2754 LLT PtrTy = MRI.getType(PtrReg);
2760 TargetOpcode::G_ZEXTLOAD, LargeLdReg, PtrReg, *LargeMMO);
2766 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2778 MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
2786 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
2817 Register PtrReg = MI.getOperand(1).getReg()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 11216 Register PtrReg = RegInfo.createVirtualRegister(RC);
11278 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
11283 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
11304 .addReg(PtrReg);
11348 .addReg(PtrReg);
12222 Register PtrReg = RegInfo.createVirtualRegister(RC);
12292 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
12297 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
12329 .addReg(PtrReg);
12353 .addReg(PtrReg);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 2621 const Register PtrReg = I.getOperand(1).getReg();
2622 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);
2626 assert(MRI.getType(PtrReg).isPointer() &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 4673 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX;
4674 SDValue Chain = CurDAG->getCopyToReg(Node->getOperand(0), dl, PtrReg,

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