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    Searched refs:QueuePtr (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUArgumentUsageInfo.cpp 68 << " QueuePtr: " << FI.second.QueuePtr
133 return std::make_tuple(QueuePtr ? &QueuePtr : nullptr,
154 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7);
SIMachineFunctionInfo.cpp 21 QueuePtr(false),
145 QueuePtr = true;
154 QueuePtr = true;
215 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
218 return ArgInfo.QueuePtr.getRegister();
530 Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
SIMachineFunctionInfo.h 183 Optional<SIArgument> QueuePtr;
207 YamlIO.mapOptional("queuePtr", AI.QueuePtr);
400 bool QueuePtr : 1;
636 return QueuePtr;
769 return ArgInfo.QueuePtr.getRegister();
AMDGPUArgumentUsageInfo.h 126 ArgDescriptor QueuePtr;
AMDGPUTargetMachine.cpp 1341 parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1342 MFI->ArgInfo.QueuePtr, 2, 0) ||
AMDGPULegalizerInfo.cpp 1766 Register QueuePtr = MRI.createGenericVirtualRegister(
1769 if (!loadInputValue(QueuePtr, B, AMDGPUFunctionArgInfo::QUEUE_PTR))
1786 B.materializePtrAdd(LoadAddr, QueuePtr, LLT::scalar(64), StructOffset);
SIISelLowering.cpp 1992 allocateSGPR64Input(CCInfo, ArgInfo.QueuePtr);
5203 SDValue QueuePtr = CreateLiveInRegister(
5207 QueuePtr, SDValue());
5283 SDValue QueuePtr = CreateLiveInRegister(
5291 DAG.getObjectPtrOffset(DL, QueuePtr, TypeSize::Fixed(StructOffset));
5297 return DAG.getLoad(MVT::i32, DL, QueuePtr.getValue(1), Ptr, PtrInfo,

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