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    Searched refs:R128_WRITE (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm/dist/shared-core/
r128_irq.c 58 R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
75 R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN);
88 * R128_WRITE(R128_GEN_INT_CNTL,
98 R128_WRITE(R128_GEN_INT_CNTL, 0);
100 R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
115 R128_WRITE(R128_GEN_INT_CNTL, 0);
r128_cce.c 120 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
187 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
189 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);
190 R128_WRITE(R128_PM4_MICROCODE_DATAL,
204 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
239 R128_WRITE(R128_PM4_BUFFER_CNTL,
243 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
254 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
255 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
265 R128_WRITE(R128_PM4_MICRO_CNTL, 0)
    [all...]
r128_drv.h 394 #define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
402 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
513 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail ); \
r128_state.c 1276 R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset);
1277 R128_WRITE(R128_CRTC_OFFSET_CNTL,
1292 R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset);
1293 R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl);
  /src/sys/external/bsd/drm2/dist/drm/r128/
r128_irq.c 65 R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
82 R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN);
95 * R128_WRITE(R128_GEN_INT_CNTL,
105 R128_WRITE(R128_GEN_INT_CNTL, 0);
107 R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
122 R128_WRITE(R128_GEN_INT_CNTL, 0);
r128_cce.c 96 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
186 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
188 R128_WRITE(R128_PM4_MICROCODE_DATAH,
190 R128_WRITE(R128_PM4_MICROCODE_DATAL,
208 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
243 R128_WRITE(R128_PM4_BUFFER_CNTL,
247 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
258 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
259 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
269 R128_WRITE(R128_PM4_MICRO_CNTL, 0)
    [all...]
r128_drv.h 410 #define R128_WRITE(reg, val) writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
418 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
534 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail); \
r128_state.c 1244 R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset);
1245 R128_WRITE(R128_CRTC_OFFSET_CNTL,
1260 R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset);
1261 R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl);

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