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    Searched refs:RADEON_WRITE (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm/dist/shared-core/
r600_cp.c 213 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
214 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
215 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
232 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
233 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
234 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
241 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
242 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
244 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
245 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a)
    [all...]
radeon_irq.c 48 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
61 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
155 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
158 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
168 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
231 RADEON_WRITE(RADEON_AIC_CNTL, tmp);
232 RADEON_WRITE(RADEON_AIC_CNTL,
239 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
240 RADEON_WRITE(RADEON_BUS_CNTL, tmp |
246 RADEON_WRITE(RADEON_MSI_REARM_EN, tmp)
    [all...]
radeon_cp.c 64 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
66 RADEON_WRITE(R520_MC_IND_INDEX, 0);
73 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
75 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
82 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
84 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
91 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
130 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
132 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
143 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc)
    [all...]
radeon_drv.h 1863 #define RADEON_WRITE(reg,val) \
1879 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
1886 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
1891 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1892 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1893 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1898 RADEON_WRITE( RS480_NB_MC_INDEX, \
1900 RADEON_WRITE( RS480_NB_MC_DATA, (val) ); \
1901 RADEON_WRITE( RS480_NB_MC_INDEX, 0xff ); \
1906 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK));
    [all...]
radeon_state.c 1933 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
1935 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
1937 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,

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