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    Searched refs:RA_ETH_SW_PCTL0 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/mips/ralink/
ralink_eth.c	1713 sw_write(sc, RA_ETH_SW_PCTL0, 1775 sw_write(sc, RA_ETH_SW_PCTL0,
ralink_reg.h	1013 #define RA_ETH_SW_PCTL0 0xC0 /* PCR0 */

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