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    Searched refs:REGWRITE_2 (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/arch/hpcmips/stand/lcboot/
i28f128.c 65 REGWRITE_2(base, 0, 0x98);
79 REGWRITE_2(base, 0, 0xff);
88 REGWRITE_2(addr, 0, I28F128_BLK_ERASE_1ST);
89 REGWRITE_2(addr, 0, I28F128_BLK_ERASE_2ND);
95 REGWRITE_2(addr, 0, I28F128_CLEAR_STATUS);
96 REGWRITE_2(addr, 0, I28F128_RESET);
108 REGWRITE_2(addr, 0, I28F128_WORDBYTE_PROG);
109 REGWRITE_2(addr, 0, data);
115 REGWRITE_2(addr, 0, I28F128_CLEAR_STATUS);
116 REGWRITE_2(addr, 0, I28F128_RESET)
    [all...]
main.c 188 REGWRITE_2(VRETIMEH, 0, 0);
189 REGWRITE_2(VRETIMEM, 0, 0);
190 REGWRITE_2(VRETIMEL, 0, 0);
213 REGWRITE_2(VR4181_ISABRG_ADDR, ISABRGCTL, 0x0003);
214 REGWRITE_2(VR4181_ISABRG_ADDR, XISACTL, 0x0401);
224 REGWRITE_2(VR4181_CMU_ADDR, 0, CMUMASK_SIU | CMUMASK_AIU);
242 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PIOD_L_REG_W, 0xffff);
243 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE0_REG_W,
256 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE1_REG_W, GP8_GPO);
268 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE2_REG_W
    [all...]
if_cs.c 75 #define CS_WRITE_2(off, val) REGWRITE_2(CS_IO_BASE, (off), (val))
77 (REGWRITE_2(CS_IO_BASE, PORT_PKTPG_PTR, (off)), \
80 (REGWRITE_2(CS_IO_BASE, PORT_PKTPG_PTR, (off)), \
81 REGWRITE_2(CS_IO_BASE, PORT_PKTPG_DATA, (val)))
extern.h 86 #define REGWRITE_2(base, off, val) \
103 #define bus_space_write_2(iot, ioh, off, val) REGWRITE_2((ioh), (off), (val))

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