HomeSort by: relevance | last modified time | path
    Searched refs:REG_BIT (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_gpu_commands.h 170 #define MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
171 #define MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/
240 #define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE REG_BIT(10) /* gen12 */
242 #define PIPE_CONTROL_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */
intel_gtt.h 90 #define GEN6_PTE_VALID REG_BIT(0)
96 #define GEN6_PDE_VALID REG_BIT(0)
101 #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)
102 #define BYT_PTE_WRITEABLE REG_BIT(1)
138 #define CHV_PPAT_SNOOP REG_BIT(6)
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 74 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
112 * #define FOO_ENABLE REG_BIT(31)
123 * REG_BIT() - Prepare a u32 bit value
130 #define REG_BIT(__n) \
161 * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
178 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
2077 #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
2522 #define RESET_CTL_CAT_ERROR REG_BIT(2)
2523 #define RESET_CTL_READY_TO_RESET REG_BIT(1)
2524 #define RESET_CTL_REQUEST_RESET REG_BIT(0
    [all...]

Completed in 26 milliseconds