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    Searched refs:REG_FIELD_GET (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_color.c 1675 blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
1677 blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
1679 blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1717 blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
1718 REG_FIELD_GET(PALETTE_RED_MASK, val1);
1719 blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
1720 REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
1721 blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
1722 REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
1725 blob_data[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK
    [all...]
intel_lvds.c 167 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
168 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
169 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
172 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
173 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
176 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
177 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
intel_dp.c 6742 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
6743 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
6744 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
6745 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
6752 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
6754 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
intel_ddi.c 4365 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 161 * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
173 * REG_FIELD_GET() - Extract a u32 bitfield value
182 #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))

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