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    Searched refs:REG_FIELD_PREP (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_lvds.c 218 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |
219 REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) |
220 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5));
223 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) |
224 REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx));
227 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
228 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK,
intel_dp.c 6914 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
6915 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
6916 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
6917 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
6950 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
6951 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
6957 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 69 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
114 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
115 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
116 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
156 * REG_FIELD_PREP() - Prepare a u32 bitfield value
165 #define REG_FIELD_PREP(__mask, __val) \
178 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
4879 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
4880 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
4881 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/uc/
intel_guc.c 147 u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);

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