| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubp.c | 89 REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value);
94 REG_GET(VBLANK_PARAMETERS_6,
101 REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value);
106 REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value);
241 REG_GET(DCHUBP_REQ_SIZE_CONFIG_C,
248 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C,
251 REG_GET(DCSURF_SURFACE_PITCH_C,
369 REG_GET(HUBPRET_CONTROL,
462 REG_GET(BLANK_OFFSET_1,
464 REG_GET(DST_DIMENSIONS
[all...] |
| amdgpu_dcn21_hwseq.c | 60 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
62 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
| amdgpu_dcn21_hubbub.c | 88 REG_GET(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, &riommu_active);
569 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A,
572 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A,
575 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A,
578 REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A,
583 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,
586 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B,
589 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B,
592 REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B,
597 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
[all...] |
| amdgpu_dcn21_link_encoder.c | 217 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &value);
228 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &value);
240 REG_GET(RDPCSTX_PHY_CNTL6,
252 REG_GET(RDPCSTX_PHY_CNTL6,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_mpc.c | 145 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);
146 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
147 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle);
159 REG_GET(MPCC_TOP_SEL[mpcc_id],
384 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
410 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux);
414 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
415 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);
416 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel);
430 REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id)
[all...] |
| amdgpu_dcn10_hubp.c | 100 REG_GET(DCHUBP_CNTL,
730 REG_GET(DCSURF_FLIP_CONTROL,
733 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
736 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
866 REG_GET(HUBPRET_CONTROL,
879 REG_GET(BLANK_OFFSET_1,
882 REG_GET(DST_DIMENSIONS,
902 REG_GET(REF_FREQ_TO_PIX_FREQ,
906 REG_GET(VBLANK_PARAMETERS_1,
909 REG_GET(VBLANK_PARAMETERS_3
[all...] |
| amdgpu_dcn10_optc.c | 589 REG_GET(OTG_STATUS_FRAME_COUNT,
637 REG_GET(OTG_NOM_VERT_POSITION,
661 REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
664 REG_GET(OTG_VERT_SYNC_CONTROL,
688 REG_GET(OTG_V_SYNC_A_CNTL,
1238 REG_GET(OTG_STEREO_STATUS,
1275 REG_GET(OTG_CONTROL,
1282 REG_GET(OTG_V_SYNC_A_CNTL,
1285 REG_GET(OTG_V_TOTAL,
1288 REG_GET(OTG_V_TOTAL_MAX
[all...] |
| amdgpu_dcn10_dpp.c | 104 REG_GET(DPP_CONTROL,
106 REG_GET(CM_IGAM_CONTROL,
108 REG_GET(CM_IGAM_CONTROL,
110 REG_GET(CM_DGAM_CONTROL,
112 REG_GET(CM_RGAM_CONTROL,
114 REG_GET(CM_GAMUT_REMAP_CONTROL,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hubp.c | 678 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status);
864 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
878 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
896 REG_GET(DCSURF_FLIP_CONTROL,
899 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
902 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
1058 REG_GET(HUBPRET_CONTROL,
1071 REG_GET(BLANK_OFFSET_1,
1074 REG_GET(DST_DIMENSIONS,
1094 REG_GET(REF_FREQ_TO_PIX_FREQ
[all...] |
| amdgpu_dcn20_stream_encoder.c | 355 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
357 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width);
358 REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp_pps_line_num);
360 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
361 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
363 REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable);
364 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
435 REG_GET(DP_SEC_METADATA_TRANSMISSION,
|
| amdgpu_dcn20_vmid.c | 63 REG_GET(PAGE_TABLE_BASE_ADDR_LO32,
|
| amdgpu_dcn20_link_encoder.c | 193 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active);
205 REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en);
206 REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow);
207 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status);
208 REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete);
|
| amdgpu_dcn20_dwb.c | 182 REG_GET(CNV_UPDATE, CNV_UPDATE_LOCK, &pre_locked);
209 REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled);
210 REG_GET(CNV_MODE, CNV_FRAME_CAPTURE_EN, &cnv_frame_capture_en);
|
| amdgpu_dcn20_dpp.c | 61 REG_GET(DPP_CONTROL,
63 REG_GET(CM_DGAM_CONTROL,
66 //REG_GET(CM_BLNDGAM_CONTROL,
68 REG_GET(CM_GAMUT_REMAP_CONTROL,
|
| amdgpu_dcn20_optc.c | 367 REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
369 REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/ |
| amdgpu_bios_parser_helper.c | 66 REG_GET(BIOS_SCRATCH_6, S6_ACC_MODE, &acc_mode);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| amdgpu_hw_gpio.c | 50 REG_GET(MASK_reg, MASK, &gpio->store.mask);
51 REG_GET(A_reg, A, &gpio->store.a);
52 REG_GET(EN_reg, EN, &gpio->store.en);
91 REG_GET(Y_reg, Y, value);
|
| amdgpu_hw_hpd.c | 84 REG_GET(int_status,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_abm.c | 100 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
101 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
104 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));
105 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
355 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
369 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
397 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
|
| amdgpu_dce_i2c_hw.c | 82 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
129 REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data);
141 REG_GET(HW_STATUS, DC_I2C_DDC1_HW_STATUS, &i2c_hw_status);
145 REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
156 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
275 REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);
353 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
|
| amdgpu_dce_aux.c | 287 *sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT,
303 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32);
321 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| amdgpu_dmub_dcn20.c | 68 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
71 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
221 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
|
| dmub_reg.h | 114 #define REG_GET(reg_name, field, val) \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_hw_sequencer.c | 262 REG_GET(MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, &pf_max_region);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/ |
| amdgpu_dce_clk_mgr.c | 143 REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
148 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
|
