| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dccg.c | 88 REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel);
|
| amdgpu_dcn20_hubp.c | 1067 REG_GET_2(BLANK_OFFSET_0,
1077 REG_GET_2(DST_AFTER_SCALER,
1082 REG_GET_2(PREFETCH_SETTINS,
1086 REG_GET_2(PREFETCH_SETTINGS,
1090 REG_GET_2(VBLANK_PARAMETERS_0,
1118 REG_GET_2(PER_LINE_DELIVERY_PRE,
1122 REG_GET_2(PER_LINE_DELIVERY,
1154 REG_GET_2(DCN_TTU_QOS_WM,
1158 REG_GET_2(DCN_GLOBAL_TTU_CNTL,
1193 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION
[all...] |
| amdgpu_dcn20_opp.c | 317 REG_GET_2(DPG_CONTROL,
|
| amdgpu_dcn20_hubbub.c | 546 REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
|
| amdgpu_dcn20_dsc.c | 239 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
264 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
|
| amdgpu_dcn20_dpp_cm.c | 926 REG_GET_2(CM_3DLUT_READ_WRITE_CONTROL,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_optc.c | 405 REG_GET_2(OTG_BLANK_CONTROL,
633 REG_GET_2(OTG_STATUS_POSITION,
1180 REG_GET_2(OTG_V_BLANK_START_END,
1278 REG_GET_2(OTG_V_BLANK_START_END,
1300 REG_GET_2(OTG_V_SYNC_A,
1304 REG_GET_2(OTG_H_BLANK_START_END,
1308 REG_GET_2(OTG_H_SYNC_A,
1340 REG_GET_2(OTG_V_BLANK_START_END,
1344 REG_GET_2(OTG_H_BLANK_START_END,
1445 REG_GET_2(OTG_CRC0_DATA_RG
[all...] |
| amdgpu_dcn10_hubp.c | 875 REG_GET_2(BLANK_OFFSET_0,
885 REG_GET_2(DST_AFTER_SCALER,
890 REG_GET_2(PREFETCH_SETTINS,
894 REG_GET_2(PREFETCH_SETTINGS,
898 REG_GET_2(VBLANK_PARAMETERS_0,
926 REG_GET_2(PER_LINE_DELIVERY_PRE,
930 REG_GET_2(PER_LINE_DELIVERY,
962 REG_GET_2(DCN_TTU_QOS_WM,
966 REG_GET_2(DCN_GLOBAL_TTU_CNTL,
1001 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION
[all...] |
| amdgpu_dcn10_mpc.c | 163 REG_GET_2(MPCC_STATUS[mpcc_id],
457 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
|
| amdgpu_dcn10_stream_encoder.c | 1573 REG_GET_2(DP_PIXEL_FORMAT,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| amdgpu_hw_ddc.c | 119 reg2 = REG_GET_2(gpio.MASK_reg,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubp.c | 244 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C,
459 REG_GET_2(BLANK_OFFSET_0,
466 REG_GET_2(DST_AFTER_SCALER,
507 REG_GET_2(PER_LINE_DELIVERY,
510 REG_GET_2(PER_LINE_DELIVERY_PRE,
580 REG_GET_2(DCN_TTU_QOS_WM,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_abm.c | 156 REG_GET_2(BL_PWM_PERIOD_CNTL,
|
| amdgpu_dce_aux.c | 480 REG_GET_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, &prev_length, AUX_RX_TIMEOUT_LEN_MUL, &prev_mult);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_resource.c | 442 REG_GET_2(CC_DC_HDMI_STRAPS,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| reg_helper.h | 162 #define REG_GET_2(reg_name, f1, v1, f2, v2) \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_resource.c | 491 REG_GET_2(CC_DC_HDMI_STRAPS,
|
| amdgpu_dce110_hw_sequencer.c | 720 REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_resource.c | 468 REG_GET_2(CC_DC_HDMI_STRAPS,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| amdgpu_dce80_resource.c | 482 REG_GET_2(CC_DC_HDMI_STRAPS,
|
