HomeSort by: relevance | last modified time | path
    Searched refs:REG_GET_3 (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
amdgpu_hw_ddc.c 92 regval = REG_GET_3(gpio.MASK_reg,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_hubp.c 256 REG_GET_3(DCSURF_SURFACE_CONFIG,
593 REG_GET_3(DCN_SURF0_TTU_CNTL0,
597 REG_GET_3(DCN_SURF1_TTU_CNTL0,
601 REG_GET_3(DCN_CUR0_TTU_CNTL0,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hubp.c 1165 REG_GET_3(DCN_SURF0_TTU_CNTL0,
1174 REG_GET_3(DCN_SURF1_TTU_CNTL0,
1207 REG_GET_3(DCHUBP_CNTL,
1495 REG_GET_3(DCN_SURF0_TTU_CNTL0,
1499 REG_GET_3(DCN_SURF1_TTU_CNTL0,
1503 REG_GET_3(DCN_CUR0_TTU_CNTL0,
amdgpu_dcn20_optc.c 297 REG_GET_3(OPTC_DATA_SOURCE_SELECT,
amdgpu_dcn20_mpc.c 498 REG_GET_3(MPCC_STATUS[mpcc_id],
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hubp.c 973 REG_GET_3(DCN_SURF0_TTU_CNTL0,
982 REG_GET_3(DCN_SURF1_TTU_CNTL0,
1015 REG_GET_3(DCHUBP_CNTL,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
reg_helper.h 167 #define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \

Completed in 18 milliseconds