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    Searched refs:REG_READ (Results 1 - 25 of 42) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
rv1_clk_mgr_clk.c 61 regs->CLK0_CLK8_CURRENT_CNT = REG_READ(CLK0_CLK8_CURRENT_CNT) / 10; //dcf clk
63 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007;
68 regs->CLK0_CLK8_DS_CNTL = REG_READ(CLK0_CLK8_DS_CNTL) / 10; //dcf deep sleep divider
70 regs->CLK0_CLK8_ALLOW_DS = REG_READ(CLK0_CLK8_ALLOW_DS); //dcf deep sleep allow
72 regs->CLK0_CLK10_CURRENT_CNT = REG_READ(CLK0_CLK10_CURRENT_CNT) / 10; //dpref clk
74 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007;
78 regs->CLK0_CLK11_CURRENT_CNT = REG_READ(CLK0_CLK11_CURRENT_CNT) / 10; //disp clk
80 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007;
amdgpu_rv1_clk_mgr_vbios_smu.c 90 return REG_READ(MP1_SMN_C2PMSG_83);
106 actual_dispclk_set_mhz = REG_READ(MP1_SMN_C2PMSG_83) * 1000;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
amdgpu_dmub_dcn21.c 63 return (REG_READ(DMCUB_SCRATCH0) == 3);
68 return REG_READ(DMCUB_SCRATCH10) == 0;
amdgpu_dmub_dcn20.c 204 return REG_READ(DMCUB_INBOX1_RPTR);
214 return REG_READ(DMCUB_REGION3_CW2_BASE_ADDRESS) != 0;
dmub_reg.h 53 #define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg)))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hubbub.c 495 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
497 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
499 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
500 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
502 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
506 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
508 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
510 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
511 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
513 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B)
    [all...]
amdgpu_dcn20_dpp.c 71 s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
72 s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
73 s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
74 s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
75 s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
76 s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
  /src/sys/arch/mips/adm5120/
adm5120_intr.c 158 #define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ADM5120_BASE_ICU + (o)))
159 #define REG_WRITE(o,v) (REG_READ(o)) = (v)
220 REG_READ(ICU_MODE_REG) | irqmask);
223 REG_READ(ICU_MODE_REG) & ~irqmask);
275 irqstat = REG_READ(ICU_FIQ_STATUS_REG);
277 irqstat = REG_READ(ICU_STATUS_REG);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_abm.c 99 pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
103 bl_pwm_cntl = REG_READ(BL_PWM_CNTL);
242 s2 = REG_READ(BIOS_SCRATCH_2);
299 unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
310 unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL);
349 REG_READ(BL_PWM_CNTL);
351 REG_READ(BL_PWM_CNTL2);
353 REG_READ(BL_PWM_PERIOD_CNTL);
391 REG_READ(BL_PWM_CNTL);
393 REG_READ(BL_PWM_CNTL2)
    [all...]
amdgpu_dce_dmcu.c 122 *psr_state = REG_READ(DMCU_IRAM_RD_DATA);
347 dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);
348 dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA);
349 dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA);
350 dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
351 REG_READ(DMCU_IRAM_RD_DATA));
393 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
420 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
451 uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15);
524 *psr_state = REG_READ(DMCU_IRAM_RD_DATA)
    [all...]
amdgpu_dce_aux.c 97 uint32_t value = REG_READ(AUX_ARB_CONTROL);
110 uint32_t value = REG_READ(AUX_ARB_CONTROL);
118 value = REG_READ(AUX_CONTROL);
163 value = REG_READ(AUX_ARB_CONTROL);
351 value = REG_READ(AUX_SW_STATUS);
amdgpu_dce_hwseq.c 87 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);
  /src/sys/dev/goldfish/
gfpic.c 54 #define REG_READ(sc, r) \
106 return ffs(REG_READ(sc, GFPIC_PENDING)) - 1;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/
amdgpu_bios_parser_helper.c 91 active_disp = REG_READ(BIOS_SCRATCH_3) & 0XFFFF;
  /src/sys/arch/virt68k/dev/
virtctrl.c 64 #define REG_READ(sc, r) \
113 feat = REG_READ(sc, VIRTCTRL_REG_FEATURES);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hubbub.c 59 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
60 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
62 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
63 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
65 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
69 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
70 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
72 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
73 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
75 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B)
    [all...]
amdgpu_dcn10_dpp.c 118 s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
119 s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
120 s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
121 s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
122 s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
123 s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
amdgpu_dcn10_stream_encoder.c 95 regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
315 misc1 = REG_READ(DP_MSA_MISC);
754 value = REG_READ(DP_SEC_CNTL);
848 value = REG_READ(DP_SEC_CNTL);
875 value = REG_READ(DP_SEC_CNTL);
1474 value = REG_READ(DP_SEC_CNTL);
  /src/sys/arch/mips/adm5120/dev/
if_admsw.c 164 #define REG_READ(o) bus_space_read_4(sc->sc_st, sc->sc_ioh, (o))
254 REG_READ(PORT_CONF0_REG) | PORT_CONF0_DP_MASK);
256 REG_READ(CPUP_CONF_REG) | CPUP_CONF_DCPUP);
267 REG_READ(PHY_CNTL2_REG) & ~PHY_CNTL2_PHYR_MASK);
284 REG_READ(PHY_CNTL2_REG) | PHY_CNTL2_ANE_MASK |
287 REG_WRITE(PHY_CNTL3_REG, REG_READ(PHY_CNTL3_REG) | PHY_CNTL3_RNT);
302 REG_READ(FC_TH_REG) & ~(FC_TH_FCS_MASK | FC_TH_D2S_MASK));
316 while (!(REG_READ(MAC_WT0_REG) & MAC_WT0_WRITE_DONE))
319 wdog1 = REG_READ(ADM5120_WDOG1);
797 pending = REG_READ(ADMSW_INT_ST)
    [all...]
uart.c 54 #define REG_READ(o) bus_space_read_4(sc->sc_st, sc->sc_ioh, (o))
339 if (REG_READ(UART_RSR_REG) & UART_RSR_BE) {
344 while ((REG_READ(UART_FR_REG) & UART_FR_RX_FIFO_EMPTY) == 0) {
345 c = REG_READ(UART_DR_REG) & 0xff;
ahci.c 244 #define REG_READ(o) bus_space_read_4(sc->sc_st, sc->sc_ioh, (o))
294 while (REG_READ(ADMHCD_REG_CONTROL) & ADMHCD_SW_RESET)
464 if ((REG_READ(ADMHCD_REG_PORTSTATUS0) & ADMHCD_CCS) != p0_state) {
467 p0_state=(REG_READ(ADMHCD_REG_PORTSTATUS0) & ADMHCD_CCS);
469 if ((REG_READ(ADMHCD_REG_PORTSTATUS1) & ADMHCD_CCS) != p1_state) {
472 p1_state=(REG_READ(ADMHCD_REG_PORTSTATUS1) & ADMHCD_CCS);
677 status = REG_READ(ADMHCD_REG_PORTSTATUS0+(index-1)*4);
873 /* printf("status: %x\n",REG_READ(ADMHCD_REG_PORTSTATUS0));
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_hwseq.c 95 value = REG_READ(MICROSECOND_TIME_BASE_DIV);
  /src/sys/external/isc/atheros_hal/dist/ar5312/
ar5312reg.h 32 #define REG_READ(_reg) *((volatile uint32_t *)(_reg))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
amdgpu_rn_clk_mgr.c 236 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
237 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);
239 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider
240 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);
242 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
243 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);
245 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
246 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);
248 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
249 internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL)
    [all...]
amdgpu_rn_clk_mgr_vbios_smu.c 75 return REG_READ(MP1_SMN_C2PMSG_83);

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