| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_opp.c | 335 REG_SET_2(FMT_CLAMP_CNTL, 0,
343 REG_SET_2(FMT_CLAMP_CNTL, 0,
348 REG_SET_2(FMT_CLAMP_CNTL, 0,
353 REG_SET_2(FMT_CLAMP_CNTL, 0,
359 REG_SET_2(FMT_CLAMP_CNTL, 0,
364 REG_SET_2(FMT_CLAMP_COMPONENT_R, 0,
368 REG_SET_2(FMT_CLAMP_COMPONENT_G, 0,
372 REG_SET_2(FMT_CLAMP_COMPONENT_B, 0,
|
| amdgpu_dce_transform.c | 136 REG_SET_2(SCL_TAP_CONTROL, 0,
177 REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0,
180 REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0,
244 REG_SET_2(VIEWPORT_START, 0,
248 REG_SET_2(VIEWPORT_SIZE, 0,
298 REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
302 REG_SET_2(SCL_VERT_FILTER_INIT, 0,
336 REG_SET_2(LB_MEMORY_CTRL, 0,
448 REG_SET_2(OUT_CLAMP_CONTROL_B_CB, 0,
452 REG_SET_2(OUT_CLAMP_CONTROL_G_Y, 0
[all...] |
| amdgpu_dce_ipp.c | 62 REG_SET_2(CUR_POSITION, 0,
66 REG_SET_2(CUR_HOT_SPOT, 0,
124 REG_SET_2(CUR_SIZE, 0,
154 REG_SET_2(PRESCALE_VALUES_GRPH_R, 0,
158 REG_SET_2(PRESCALE_VALUES_GRPH_G, 0,
162 REG_SET_2(PRESCALE_VALUES_GRPH_B, 0,
|
| amdgpu_dce_hwseq.c | 76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
81 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
|
| amdgpu_dce_mem_input.c | 177 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,
191 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,
195 REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0,
456 REG_SET_2(GRPH_SWAP_CNTL, 0,
662 REG_SET_2(GRPH_SECONDARY_SURFACE_ADDRESS, 0,
|
| amdgpu_dce_i2c_hw.c | 239 value = REG_SET_2(DC_I2C_DATA, 0,
247 REG_SET_2(DC_I2C_DATA, value,
|
| amdgpu_dce_stream_encoder.c | 474 REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
501 REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
518 REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
733 REG_SET_2(DP_MSE_RATE_CNTL, 0,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_opp.c | 96 REG_SET_2(DPG_DIMENSIONS, 0,
170 REG_SET_2(DPG_COLOUR_R_CR, 0,
173 REG_SET_2(DPG_COLOUR_G_Y, 0,
176 REG_SET_2(DPG_COLOUR_B_CB, 0,
281 REG_SET_2(DPG_DIMENSIONS, 0,
300 REG_SET_2(DPG_COLOUR_B_CB, 0,
303 REG_SET_2(DPG_COLOUR_G_Y, 0,
306 REG_SET_2(DPG_COLOUR_R_CR, 0,
|
| amdgpu_dcn20_vmid.c | 90 REG_SET_2(CNTL, 0,
|
| amdgpu_dcn20_dccg.c | 69 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
|
| amdgpu_dcn20_dpp_cm.c | 587 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0,
590 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0,
593 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0,
597 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0,
601 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0,
605 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0,
737 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0,
740 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0,
743 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0,
747 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0
[all...] |
| amdgpu_dcn20_optc.c | 134 REG_SET_2(OTG_GSL_WINDOW_X, 0,
137 REG_SET_2(OTG_GSL_WINDOW_Y, 0,
187 REG_SET_2(OTG_DSC_START_POSITION, 0,
254 * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
|
| amdgpu_dcn20_stream_encoder.c | 178 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0,
188 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0,
198 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0,
208 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0,
|
| amdgpu_dcn20_hubp.c | 79 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
92 REG_SET_2(BLANK_OFFSET_0, 0,
102 REG_SET_2(DST_AFTER_SCALER, 0,
127 REG_SET_2(PER_LINE_DELIVERY, 0,
149 REG_SET_2(DCN_TTU_QOS_WM, 0,
254 REG_SET_2(PREFETCH_SETTINGS, 0,
261 REG_SET_2(VBLANK_PARAMETERS_0, 0,
265 REG_SET_2(FLIP_PARAMETERS_0, 0,
278 REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
293 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0
[all...] |
| amdgpu_dcn20_dsc.c | 558 REG_SET_2(DSCCIF_CONFIG1, 0,
571 /*REG_SET_2(DSCC_CONFIG1, 0,
600 REG_SET_2(DSCC_PPS_CONFIG2, 0,
604 REG_SET_2(DSCC_PPS_CONFIG3, 0,
611 REG_SET_2(DSCC_PPS_CONFIG5, 0,
620 REG_SET_2(DSCC_PPS_CONFIG7, 0,
624 REG_SET_2(DSCC_PPS_CONFIG8, 0,
628 REG_SET_2(DSCC_PPS_CONFIG9, 0,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_dpp_dscl.c | 112 REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0,
116 REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0,
129 REG_SET_2(OTG_H_BLANK, 0,
133 REG_SET_2(OTG_V_BLANK, 0,
228 REG_SET_2(LB_DATA_FORMAT, 0,
233 REG_SET_2(LB_MEMORY_CTRL, 0,
391 REG_SET_2(SCL_MODE, scl_mode,
563 REG_SET_2(SCL_BLACK_OFFSET, 0,
568 REG_SET_2(SCL_BLACK_OFFSET, 0,
605 REG_SET_2(SCL_HORZ_FILTER_INIT, 0
[all...] |
| amdgpu_dcn10_hubp.c | 587 REG_SET_2(BLANK_OFFSET_0, 0,
597 REG_SET_2(DST_AFTER_SCALER, 0,
622 REG_SET_2(PER_LINE_DELIVERY, 0,
644 REG_SET_2(DCN_TTU_QOS_WM, 0,
689 REG_SET_2(PREFETCH_SETTINS, 0,
696 REG_SET_2(VBLANK_PARAMETERS_0, 0,
706 REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
719 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
763 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0,
803 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0
[all...] |
| amdgpu_dcn10_cm_common.c | 61 REG_SET_2(cur_csc_reg, 0,
78 REG_SET_2(reg->start_cntl_b, 0,
81 REG_SET_2(reg->start_cntl_g, 0,
84 REG_SET_2(reg->start_cntl_r, 0,
97 REG_SET_2(reg->start_end_cntl2_b, 0,
103 REG_SET_2(reg->start_end_cntl2_g, 0,
109 REG_SET_2(reg->start_end_cntl2_r, 0,
|
| amdgpu_dcn10_optc.c | 87 REG_SET_2(OTG_VUPDATE_PARAM, 0,
102 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0,
114 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
814 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
1057 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1069 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
|
| amdgpu_dcn10_stream_encoder.c | 433 REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
457 REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
472 REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
641 REG_SET_2(DP_MSE_RATE_CNTL, 0,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| amdgpu_dmub_dcn20.c | 118 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
127 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
152 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
161 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
170 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
179 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
188 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
|
| dmub_reg.h | 67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubbub.c | 164 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
202 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,
241 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,
280 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0,
332 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,
347 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,
363 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,
378 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,
394 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,
409 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0
[all...] |
| amdgpu_dcn21_hubp.c | 183 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
187 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
192 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
196 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
201 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
205 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
209 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
213 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
350 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| amdgpu_hw_ddc.c | 106 REG_SET_2(gpio.MASK_reg, regval,
|
