| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_ipp.c | 109 REG_SET_3(CUR_COLOR1, 0,
114 REG_SET_3(CUR_COLOR2, 0,
194 REG_SET_3(DC_LUT_CONTROL, 0,
233 REG_SET_3(DEGAMMA_CONTROL, 0,
|
| amdgpu_dce_abm.c | 267 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0,
272 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0,
290 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0,
|
| amdgpu_dce_i2c_hw.c | 115 REG_SET_3(DC_I2C_DATA, 0,
|
| amdgpu_dce_link_encoder.c | 179 REG_SET_3(DP_DPHY_SYM0, 0,
187 REG_SET_3(DP_DPHY_SYM1, 0,
|
| amdgpu_dce_transform.c | 215 REG_SET_3(SCL_COEF_RAM_SELECT, 0,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_opp.c | 222 REG_SET_3(DPG_RAMP_CONTROL, 0,
233 REG_SET_3(DPG_RAMP_CONTROL, 0,
244 REG_SET_3(DPG_RAMP_CONTROL, 0,
|
| amdgpu_dcn20_optc.c | 152 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
226 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
277 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
|
| amdgpu_dcn20_dsc.c | 581 REG_SET_3(DSCC_PPS_CONFIG0, 0,
615 REG_SET_3(DSCC_PPS_CONFIG6, 0,
632 REG_SET_3(DSCC_PPS_CONFIG10, 0,
|
| amdgpu_dcn20_dwb_scl.c | 706 REG_SET_3(WBSCL_COEF_RAM_SELECT, 0,
|
| amdgpu_dcn20_hubp.c | 156 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
161 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
166 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
654 REG_SET_3(DMDATA_QOS_CNTL, 0,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| dmub_reg.h | 72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_dpp_dscl.c | 274 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0,
556 REG_SET_3(DSCL_AUTOCAL, 0,
687 REG_SET_3(DSCL_AUTOCAL, 0,
|
| amdgpu_dcn10_dpp.c | 323 REG_SET_3(FORMAT_CONTROL, 0,
329 REG_SET_3(FORMAT_CONTROL, 0,
|
| amdgpu_dcn10_optc.c | 508 REG_SET_3(OTG_BLACK_COLOR, 0,
692 REG_SET_3(OTG_TRIGA_CNTL, 0,
701 REG_SET_3(OTG_TRIGA_CNTL, 0,
|
| amdgpu_dcn10_hubp.c | 651 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
656 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
661 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
|
| amdgpu_dcn10_link_encoder.c | 151 REG_SET_3(DP_DPHY_SYM0, 0,
159 REG_SET_3(DP_DPHY_SYM1, 0,
|
| amdgpu_dcn10_dpp_cm.c | 719 REG_SET_3(FORMAT_CONTROL, 0,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| reg_helper.h | 74 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \
|
