| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dpp_cm.c | 610 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,
617 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,
624 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,
631 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,
638 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,
645 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,
652 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,
659 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,
666 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,
673 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0
[all...] |
| amdgpu_dcn20_stream_encoder.c | 173 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
183 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
193 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
203 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
249 REG_SET_4(AFMT_GENERIC_HDR, 0,
|
| amdgpu_dcn20_dsc.c | 563 REG_SET_4(DSCC_CONFIG0, 0,
575 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0,
644 REG_SET_4(DSCC_PPS_CONFIG12, 0,
650 REG_SET_4(DSCC_PPS_CONFIG13, 0,
656 REG_SET_4(DSCC_PPS_CONFIG14, 0,
736 REG_SET_4(DSCC_TEST_DEBUG_BUS_ROTATE, 0,
|
| amdgpu_dcn20_dwb_scl.c | 711 REG_SET_4(WBSCL_COEF_RAM_TAP_DATA, 0,
|
| amdgpu_dcn20_hubp.c | 205 REG_SET_4(DCN_EXPANSION_MODE, 0,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_transform.c | 227 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
1235 REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0,
1242 REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0,
1249 REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0,
1256 REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0,
1263 REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0,
1270 REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0,
1277 REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0,
1284 REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0,
|
| amdgpu_dce_i2c_hw.c | 232 value = REG_SET_4(DC_I2C_DATA, 0,
|
| amdgpu_dce_stream_encoder.c | 115 REG_SET_4(AFMT_GENERIC_HDR, 0,
506 REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| dmub_reg.h | 78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_dpp_dscl.c | 287 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
572 REG_SET_4(SCL_TAP_CONTROL, 0,
732 REG_SET_4(SCL_TAP_CONTROL, 0,
|
| amdgpu_dcn10_stream_encoder.c | 102 REG_SET_4(AFMT_GENERIC_HDR, 0,
461 REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
802 REG_SET_4(AFMT_GENERIC_HDR, 0,
|
| amdgpu_dcn10_optc.c | 737 REG_SET_4(OTG_TRIGA_CNTL, 0,
1150 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
|
| amdgpu_dcn10_cm_common.c | 120 REG_SET_4(reg_region_cur, 0,
|
| amdgpu_dcn10_hubp.c | 553 REG_SET_4(DCN_EXPANSION_MODE, 0,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubp.c | 135 REG_SET_4(DCN_EXPANSION_MODE, 0,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| reg_helper.h | 80 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \
|
