| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_mmhubbub.c | 88 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, params->swlock);
91 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));
92 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0]));
94 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, 0);
97 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0]));
98 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0]));
100 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, 0);
103 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1]));
104 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1]));
106 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, 0)
[all...] |
| amdgpu_dcn20_dwb.c | 88 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 1);
89 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_X, params->cnv_params.crop_x);
90 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_Y, params->cnv_params.crop_y);
91 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, params->cnv_params.crop_width);
92 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, params->cnv_params.crop_height);
94 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 0);
98 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_RATE, params->capture_rate);
101 REG_UPDATE(CNV_MODE, CNV_OUT_BPC, params->cnv_params.cnv_out_bpc);
123 REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
132 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE)
[all...] |
| amdgpu_dcn20_stream_encoder.c | 88 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
95 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
102 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
109 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
116 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
123 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
130 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
137 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
156 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
230 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 1)
[all...] |
| amdgpu_dcn20_dpp.c | 86 REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0);
88 REG_UPDATE(OBUF_MEM_PWR_CTRL,
91 REG_UPDATE(DSCL_MEM_PWR_CTRL,
127 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
128 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
129 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
130 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
216 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
217 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
218 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2)
[all...] |
| amdgpu_dcn20_optc.c | 60 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
64 REG_UPDATE(CONTROL,
91 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
124 REG_UPDATE(OTG_GSL_CONTROL,
167 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal);
170 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal);
173 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal);
204 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
210 REG_UPDATE(OPTC_WIDTH_CONTROL,
233 REG_UPDATE(OTG_H_TIMING_CNTL
[all...] |
| amdgpu_dcn20_dwb_scl.c | 756 REG_UPDATE(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, h_ratio_luma);
759 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, h_taps_luma - 1);
760 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, h_taps_chroma - 1);
782 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, h_init_phase_luma_int);
783 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, h_init_phase_luma_frac);
784 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, h_init_phase_chroma_int);
785 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, h_init_phase_chroma_frac);
834 REG_UPDATE(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, v_ratio_luma);
837 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, v_taps_luma - 1);
838 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, v_taps_chroma - 1)
[all...] |
| amdgpu_dcn20_hubbub.c | 420 REG_UPDATE(DCN_VM_FB_LOCATION_TOP,
423 REG_UPDATE(DCN_VM_FB_LOCATION_BASE,
427 REG_UPDATE(DCN_VM_AGP_BASE,
432 REG_UPDATE(DCN_VM_AGP_BOT,
437 REG_UPDATE(DCN_VM_AGP_TOP,
445 REG_UPDATE(DCN_VM_AGP_BASE,
450 REG_UPDATE(DCN_VM_AGP_BOT,
455 REG_UPDATE(DCN_VM_AGP_TOP,
463 REG_UPDATE(DCN_VM_AGP_BASE,
468 REG_UPDATE(DCN_VM_AGP_BOT
[all...] |
| amdgpu_dcn20_dccg.c | 72 REG_UPDATE(DPPCLK_DTO_CTRL,
75 REG_UPDATE(DPPCLK_DTO_CTRL,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| amdgpu_hw_gpio.c | 59 REG_UPDATE(MASK_reg, MASK, gpio->store.mask);
60 REG_UPDATE(A_reg, A, gpio->store.a);
61 REG_UPDATE(EN_reg, EN, gpio->store.en);
112 REG_UPDATE(A_reg, A, value);
119 REG_UPDATE(EN_reg, EN, ~value);
156 REG_UPDATE(EN_reg, EN, 0);
157 REG_UPDATE(MASK_reg, MASK, 1);
162 REG_UPDATE(A_reg, A, 0);
163 REG_UPDATE(MASK_reg, MASK, 1);
168 REG_UPDATE(A_reg, A, 0)
[all...] |
| amdgpu_hw_ddc.c | 154 REG_UPDATE(gpio.MASK_reg,
159 REG_UPDATE(dc_gpio_aux_ctrl_5, DDC_PAD_I2CMODE, 1);
163 REG_UPDATE(phy_aux_cntl, AUX_PAD_RXSEL, 1);
173 REG_UPDATE(dc_gpio_aux_ctrl_5,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_stream_encoder.c | 83 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
103 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
108 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
149 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
153 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
157 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
161 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
165 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
169 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
173 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1
[all...] |
| amdgpu_dce_dmcu.c | 114 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
127 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
146 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
149 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
153 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
196 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
200 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
204 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
208 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
225 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK
[all...] |
| amdgpu_dce_ipp.c | 56 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);
60 REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable);
71 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);
82 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);
141 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);
151 REG_UPDATE(PRESCALE_GRPH_CONTROL,
167 REG_UPDATE(PRESCALE_GRPH_CONTROL,
171 REG_UPDATE(INPUT_GAMMA_CONTROL,
191 REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0);
220 REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1)
[all...] |
| amdgpu_dce_hwseq.c | 48 REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst],
122 REG_UPDATE(BLND_CONTROL[blnd_inst],
137 REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL,
145 REG_UPDATE(DCFEV_CLOCK_CONTROL,
176 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
186 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
197 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
|
| amdgpu_dce_abm.c | 83 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
193 REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit);
196 REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
228 REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_pwm_u16_16);
236 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET);
239 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
277 REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL,
280 REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL,
283 REG_UPDATE(BL1_PWM_USER_LEVEL,
334 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1)
[all...] |
| amdgpu_dce_opp.c | 180 REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
213 REG_UPDATE(FMT_DITHER_RAND_R_SEED,
216 REG_UPDATE(FMT_DITHER_RAND_G_SEED,
219 REG_UPDATE(FMT_DITHER_RAND_B_SEED,
309 REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
318 REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
448 REG_UPDATE(FMT_CONTROL,
452 REG_UPDATE(CONTROL,
501 REG_UPDATE(FMT_CONTROL,
|
| amdgpu_dce_mem_input.c | 155 REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT,
174 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
188 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
207 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
215 REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
220 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
228 REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL,
239 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
257 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
261 REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_stream_encoder.c | 73 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
92 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
96 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
128 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
132 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
136 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
140 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
144 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
148 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
152 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1
[all...] |
| amdgpu_dcn10_opp.c | 173 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
182 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);
297 REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0);
331 REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0);
333 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, active_width);
341 REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, space2_size);
343 REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, space1_size);
347 REG_UPDATE(OPPBUF_3D_PARAMETERS_0,
349 REG_UPDATE(OPPBUF_3D_PARAMETERS_1,
351 REG_UPDATE(OPPBUF_3D_PARAMETERS_1
[all...] |
| dcn10_dwb.c | 83 REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
93 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, 0);
96 REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);
99 REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1);
100 REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0);
|
| amdgpu_dcn10_dpp.c | 285 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
286 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
288 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
289 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
400 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
421 REG_UPDATE(CURSOR_CONTROL,
423 REG_UPDATE(CURSOR0_CONTROL,
441 REG_UPDATE(CURSOR0_COLOR0,
443 REG_UPDATE(CURSOR0_COLOR1,
486 REG_UPDATE(CURSOR0_CONTROL
[all...] |
| amdgpu_dcn10_hubp.c | 79 REG_UPDATE(DCHUBP_CNTL,
82 REG_UPDATE(CURSOR_CONTROL,
91 REG_UPDATE(DCHUBP_CNTL,
112 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
120 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en);
266 REG_UPDATE(DCSURF_SURFACE_CONFIG,
270 REG_UPDATE(DCSURF_SURFACE_CONFIG,
275 REG_UPDATE(DCSURF_SURFACE_CONFIG,
281 REG_UPDATE(DCSURF_SURFACE_CONFIG,
285 REG_UPDATE(DCSURF_SURFACE_CONFIG
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_hw_sequencer.c | 213 REG_UPDATE(DCHUB_AGP_BASE,
216 REG_UPDATE(DCHUB_AGP_BOT,
219 REG_UPDATE(DCHUB_AGP_TOP,
224 REG_UPDATE(DCHUB_AGP_BASE,
227 REG_UPDATE(DCHUB_AGP_BOT,
230 REG_UPDATE(DCHUB_AGP_TOP,
235 REG_UPDATE(DCHUB_AGP_BASE,
238 REG_UPDATE(DCHUB_AGP_BOT,
241 REG_UPDATE(DCHUB_AGP_TOP,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/ |
| amdgpu_bios_parser_helper.c | 74 REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, 1);
83 REG_UPDATE(BIOS_SCRATCH_6, S6_CRITICAL_STATE, critial_state);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| amdgpu_dmub_dcn20.c | 85 REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
86 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
87 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
94 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
97 REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
109 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
|
