| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_opp.c | 84 REG_UPDATE_2(FMT_CONTROL,
88 REG_UPDATE_2(FMT_CONTROL,
95 REG_UPDATE_2(FMT_CONTROL,
202 REG_UPDATE_2(FMT_CLAMP_CNTL,
208 REG_UPDATE_2(FMT_CLAMP_CNTL,
213 REG_UPDATE_2(FMT_CLAMP_CNTL,
218 REG_UPDATE_2(FMT_CLAMP_CNTL,
224 REG_UPDATE_2(FMT_CLAMP_CNTL,
244 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
259 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL
[all...] |
| amdgpu_dcn10_optc.c | 181 REG_UPDATE_2(OTG_H_SYNC_A,
195 REG_UPDATE_2(OTG_H_BLANK_START_END,
222 REG_UPDATE_2(OTG_V_SYNC_A,
236 REG_UPDATE_2(OTG_V_BLANK_START_END,
270 REG_UPDATE_2(OTG_CONTROL,
337 REG_UPDATE_2(CONTROL,
360 REG_UPDATE_2(OTG_BLANK_CONTROL,
383 REG_UPDATE_2(OTG_BLANK_CONTROL,
417 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
426 REG_UPDATE_2(OTG_CLOCK_CONTROL
[all...] |
| amdgpu_dcn10_stream_encoder.c | 349 REG_UPDATE_2(DP_PIXEL_FORMAT,
533 REG_UPDATE_2(HDMI_CONTROL,
537 REG_UPDATE_2(HDMI_CONTROL,
544 REG_UPDATE_2(HDMI_CONTROL,
548 REG_UPDATE_2(HDMI_CONTROL,
554 REG_UPDATE_2(HDMI_CONTROL,
567 REG_UPDATE_2(HDMI_CONTROL,
579 REG_UPDATE_2(HDMI_CONTROL,
971 REG_UPDATE_2(DP_VID_TIMING,
1316 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2
[all...] |
| amdgpu_dcn10_hubp.c | 51 REG_UPDATE_2(DCHUBP_CNTL,
200 REG_UPDATE_2(DCSURF_SURFACE_PITCH,
204 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
224 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
228 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
232 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
236 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
258 REG_UPDATE_2(HUBPRET_CONTROL,
384 REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
1121 REG_UPDATE_2(CURSOR_SIZE
[all...] |
| amdgpu_dcn10_link_encoder.c | 276 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
296 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
536 REG_UPDATE_2(DP_SEC_CNTL1,
1230 REG_UPDATE_2(DP_MSE_SAT0,
1244 REG_UPDATE_2(DP_MSE_SAT0,
1258 REG_UPDATE_2(DP_MSE_SAT1,
1272 REG_UPDATE_2(DP_MSE_SAT1,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_opp.c | 195 REG_UPDATE_2(FMT_CONTROL,
199 REG_UPDATE_2(FMT_CONTROL,
205 REG_UPDATE_2(FMT_CONTROL,
279 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
398 REG_UPDATE_2(FMT_CONTROL,
403 REG_UPDATE_2(FMT_CONTROL,
464 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
475 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
480 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
485 REG_UPDATE_2(
[all...] |
| amdgpu_dce_stream_encoder.c | 141 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
458 REG_UPDATE_2(
600 REG_UPDATE_2(HDMI_CONTROL,
604 REG_UPDATE_2(HDMI_CONTROL,
611 REG_UPDATE_2(HDMI_CONTROL,
615 REG_UPDATE_2(HDMI_CONTROL,
621 REG_UPDATE_2(HDMI_CONTROL,
635 REG_UPDATE_2(HDMI_CONTROL,
647 REG_UPDATE_2(HDMI_CONTROL,
773 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0
[all...] |
| amdgpu_dce_hwseq.c | 182 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
192 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst],
|
| amdgpu_dce_abm.c | 78 REG_UPDATE_2(MASTER_COMM_CMD_REG,
188 REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK,
286 REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES,
329 REG_UPDATE_2(MASTER_COMM_CMD_REG,
|
| amdgpu_dce_mem_input.c | 163 REG_UPDATE_2(DVMM_PTE_ARB_CONTROL,
243 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL2,
247 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
284 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
313 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
346 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
498 REG_UPDATE_2(GRPH_CONTROL,
|
| amdgpu_dce_dmcu.c | 88 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
100 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
339 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
354 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
473 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
485 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
|
| amdgpu_dce_link_encoder.c | 307 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
327 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
548 REG_UPDATE_2(DP_SEC_CNTL1,
1263 REG_UPDATE_2(DP_MSE_SAT0,
1277 REG_UPDATE_2(DP_MSE_SAT0,
1291 REG_UPDATE_2(DP_MSE_SAT1,
1305 REG_UPDATE_2(DP_MSE_SAT1,
|
| amdgpu_dce_i2c_hw.c | 263 REG_UPDATE_2(DC_I2C_CONTROL,
359 REG_UPDATE_2(DC_I2C_CONTROL,
368 REG_UPDATE_2(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_stream_encoder.c | 85 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
92 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
99 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
106 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
113 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
120 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
127 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
134 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
287 REG_UPDATE_2(DP_DSC_CNTL,
325 REG_UPDATE_2(DP_MSA_VBID_MISC
[all...] |
| amdgpu_dcn20_opp.c | 226 REG_UPDATE_2(DPG_CONTROL,
237 REG_UPDATE_2(DPG_CONTROL,
248 REG_UPDATE_2(DPG_CONTROL,
277 REG_UPDATE_2(DPG_CONTROL,
|
| amdgpu_dcn20_optc.c | 70 REG_UPDATE_2(OTG_CONTROL,
364 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1,
371 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
382 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
388 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0,
|
| amdgpu_dcn20_mpc.c | 124 REG_UPDATE_2(DENORM_CONTROL[opp_id],
127 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id],
130 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id],
295 REG_UPDATE_2(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id],
|
| amdgpu_dcn20_hubp.c | 66 REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
364 REG_UPDATE_2(DCSURF_SURFACE_PITCH,
369 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
389 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
393 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
397 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
401 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
437 REG_UPDATE_2(HUBPRET_CONTROL,
592 REG_UPDATE_2(CURSOR_SIZE,
726 REG_UPDATE_2(DCSURF_SURFACE_CONTROL
[all...] |
| amdgpu_dcn20_dwb.c | 83 REG_UPDATE_2(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, params->cnv_params.src_width,
261 REG_UPDATE_2(WBSCL_MODE, WBSCL_MODE, params->out_format,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| amdgpu_hw_generic.c | 81 REG_UPDATE_2(mux,
|
| amdgpu_hw_hpd.c | 105 REG_UPDATE_2(toggle_filt_cntl,
|
| amdgpu_hw_ddc.c | 201 REG_UPDATE_2(ddc_setup,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| amdgpu_dmub_dcn20.c | 96 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
110 REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
131 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
|
| dmub_reg.h | 94 #define REG_UPDATE_2(reg, f1, v1, f2, v2) \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_hw_sequencer.c | 209 REG_UPDATE_2(DCHUB_FB_LOCATION,
|
