| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_opp.c | 116 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
125 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
131 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
141 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
170 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
175 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
242 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
252 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
274 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
283 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL
[all...] |
| amdgpu_dce_stream_encoder.c | 216 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
222 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
228 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
234 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
242 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
249 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
256 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
263 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
581 REG_UPDATE_3(HDMI_CONTROL,
653 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL
[all...] |
| amdgpu_dce_hwseq.c | 126 REG_UPDATE_3(BLND_CONTROL[blnd_inst],
|
| amdgpu_dce_mem_input.c | 158 REG_UPDATE_3(DVMM_PTE_CONTROL,
210 REG_UPDATE_3(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
223 REG_UPDATE_3(DPG_PIPE_LOW_POWER_CONTROL,
|
| amdgpu_dce_ipp.c | 103 REG_UPDATE_3(CUR_CONTROL,
|
| amdgpu_dce_link_encoder.c | 406 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
442 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| amdgpu_hw_ddc.c | 181 REG_UPDATE_3(ddc_setup,
191 REG_UPDATE_3(ddc_setup,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_stream_encoder.c | 194 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
200 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
206 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
212 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
218 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
224 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
230 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
236 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
585 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
1321 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL
[all...] |
| amdgpu_dcn10_opp.c | 60 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
176 REG_UPDATE_3(FMT_CONTROL,
|
| amdgpu_dcn10_link_encoder.c | 377 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
413 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
|
| amdgpu_dcn10_optc.c | 1200 REG_UPDATE_3(OTG_STEREO_CONTROL,
1425 REG_UPDATE_3(OTG_CRC_CNTL,
|
| amdgpu_dcn10_dpp_cm.c | 789 REG_UPDATE_3(
|
| amdgpu_dcn10_hubp.c | 1125 REG_UPDATE_3(CURSOR_CONTROL,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| dmub_reg.h | 99 #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_stream_encoder.c | 392 REG_UPDATE_3(DP_SEC_METADATA_TRANSMISSION,
397 REG_UPDATE_3(HDMI_METADATA_PACKET_CONTROL,
|
| amdgpu_dcn20_dpp.c | 363 REG_UPDATE_3(CURSOR0_CONTROL,
|
| amdgpu_dcn20_hubp.c | 317 REG_UPDATE_3(DCSURF_ADDR_CONFIG,
626 REG_UPDATE_3(DMDATA_CNTL,
645 REG_UPDATE_3(DMDATA_SW_CNTL,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubp.c | 702 REG_UPDATE_3(DCSURF_FLIP_CONTROL,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| reg_helper.h | 241 #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \
|
