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    Searched refs:REG_UPDATE_4 (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
dmub_reg.h 105 #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_opp.c 258 REG_UPDATE_4(DPG_CONTROL,
amdgpu_dcn20_hubp.c 322 REG_UPDATE_4(DCSURF_TILING_CONFIG,
413 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
596 REG_UPDATE_4(CURSOR_CONTROL,
753 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_dmcu.c 187 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
606 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
amdgpu_dce_aux.c 240 value = REG_UPDATE_4(AUX_SW_DATA,
amdgpu_dce_mem_input.c 502 REG_UPDATE_4(PRESCALE_GRPH_CONTROL,
amdgpu_dce_link_encoder.c 159 REG_UPDATE_4(DP_DPHY_CNTL,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_optc.c 897 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
974 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1074 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
amdgpu_dcn10_hubp.c 161 REG_UPDATE_4(DCSURF_TILING_CONFIG,
411 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
521 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
amdgpu_dcn10_link_encoder.c 131 REG_UPDATE_4(DP_DPHY_CNTL,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_hubbub.c 104 REG_UPDATE_4(DCHVM_CLK_CTRL,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
reg_helper.h 247 #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \

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