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    Searched refs:REG_UPDATE_5 (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_dwb.c 79 REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1,
103 REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0,
amdgpu_dcn10_optc.c 886 REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
1113 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1123 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1133 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
amdgpu_dcn10_mpc.c 82 REG_UPDATE_5(MPCC_CONTROL[mpcc_id],
amdgpu_dcn10_stream_encoder.c 1015 REG_UPDATE_5(HDMI_CONTROL,
1464 REG_UPDATE_5(DP_SEC_CNTL,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_i2c_hw.c 59 REG_UPDATE_5(DC_I2C_CONTROL,
188 REG_UPDATE_5(DC_I2C_TRANSACTION0,
196 REG_UPDATE_5(DC_I2C_TRANSACTION1,
204 REG_UPDATE_5(DC_I2C_TRANSACTION2,
212 REG_UPDATE_5(DC_I2C_TRANSACTION3,
amdgpu_dce_stream_encoder.c 586 REG_UPDATE_5(HDMI_CONTROL,
1052 REG_UPDATE_5(HDMI_CONTROL,
1528 REG_UPDATE_5(DP_SEC_CNTL,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_optc.c 109 REG_UPDATE_5(OTG_GSL_CONTROL,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
reg_helper.h 254 #define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \

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