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    Searched refs:REG_UPDATE_6 (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_opp.c 122 REG_UPDATE_6(DPG_CONTROL,
181 REG_UPDATE_6(DPG_CONTROL,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_opp.c 128 REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL,
amdgpu_dcn10_mpc.c 100 REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id],
amdgpu_dcn10_stream_encoder.c 518 REG_UPDATE_6(HDMI_CONTROL,
1374 REG_UPDATE_6(AFMT_60958_2,
amdgpu_dcn10_dpp_dscl.c 328 REG_UPDATE_6(DSCL_2TAP_CONTROL,
amdgpu_dcn10_hubp.c 153 REG_UPDATE_6(DCSURF_ADDR_CONFIG,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_i2c_hw.c 309 REG_UPDATE_6(DC_I2C_CONTROL,
amdgpu_dce_mem_input.c 364 REG_UPDATE_6(GRPH_CONTROL,
amdgpu_dce_stream_encoder.c 1439 REG_UPDATE_6(AFMT_60958_2,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
reg_helper.h 262 #define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \

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