| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_dmcu.c | 92 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
116 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
140 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
234 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
311 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
343 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
365 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
378 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
401 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
417 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800)
[all...] |
| amdgpu_dce_abm.c | 71 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
85 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
200 REG_WAIT(BL_PWM_GRP1_REG_LOCK,
224 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
252 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
325 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
|
| amdgpu_dce_aux.c | 144 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1,
155 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0,
219 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
348 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,
|
| amdgpu_dce_opp.c | 505 REG_WAIT(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, 1, 10, 10);
|
| amdgpu_dce_mem_input.c | 602 REG_WAIT(DMIF_BUFFER_CONTROL,
639 REG_WAIT(DMIF_BUFFER_CONTROL,
|
| amdgpu_dce_stream_encoder.c | 92 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
96 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
741 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
960 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
1496 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
|
| amdgpu_dce_transform.c | 206 REG_WAIT(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, 0, 1, 10);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/ |
| amdgpu_rv1_clk_mgr_vbios_smu.c | 87 REG_WAIT(MP1_SMN_C2PMSG_91, CONTENT, 1, 10, 200000);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
| amdgpu_rn_clk_mgr_vbios_smu.c | 72 REG_WAIT(MP1_SMN_C2PMSG_91, CONTENT, 1, 10, 200000);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hwseq.c | 355 REG_WAIT(DOMAIN16_PG_STATUS,
363 REG_WAIT(DOMAIN17_PG_STATUS,
371 REG_WAIT(DOMAIN18_PG_STATUS,
379 REG_WAIT(DOMAIN19_PG_STATUS,
387 REG_WAIT(DOMAIN20_PG_STATUS,
395 REG_WAIT(DOMAIN21_PG_STATUS,
426 REG_WAIT(DOMAIN1_PG_STATUS,
434 REG_WAIT(DOMAIN3_PG_STATUS,
442 REG_WAIT(DOMAIN5_PG_STATUS,
450 REG_WAIT(DOMAIN7_PG_STATUS
[all...] |
| amdgpu_dcn20_stream_encoder.c | 238 /*REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 0, 10, max_retries);*/
241 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
498 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
|
| amdgpu_dcn20_optc.c | 339 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
|
| amdgpu_dcn20_mpc.c | 485 REG_WAIT(MPCC_STATUS[id],
|
| amdgpu_dcn20_hubp.c | 933 REG_WAIT(DCHUBP_CNTL,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_optc.c | 421 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
429 REG_WAIT(OTG_CLOCK_CONTROL,
494 REG_WAIT(OTG_CLOCK_CONTROL,
614 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
769 REG_WAIT(OTG_STATUS,
775 REG_WAIT(OTG_STATUS,
|
| amdgpu_dcn10_stream_encoder.c | 81 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
85 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
648 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
773 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING,
786 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
829 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING,
917 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
1432 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
|
| amdgpu_dcn10_mpc.c | 113 REG_WAIT(MPCC_STATUS[id],
|
| amdgpu_dcn10_hw_sequencer.c | 556 REG_WAIT(DOMAIN1_PG_STATUS,
564 REG_WAIT(DOMAIN3_PG_STATUS,
572 REG_WAIT(DOMAIN5_PG_STATUS,
580 REG_WAIT(DOMAIN7_PG_STATUS,
608 REG_WAIT(DOMAIN0_PG_STATUS,
616 REG_WAIT(DOMAIN2_PG_STATUS,
624 REG_WAIT(DOMAIN4_PG_STATUS,
632 REG_WAIT(DOMAIN6_PG_STATUS,
|
| amdgpu_dcn10_hubp.c | 65 REG_WAIT(DCHUBP_CNTL,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/ |
| amdgpu_dcn20_clk_mgr.c | 144 // REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100);
147 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubbub.c | 111 REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| reg_helper.h | 220 #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \
|
