1 /* $NetBSD: wdc.c,v 1.316 2026/08/07 02:25:54 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * CODE UNTESTED IN THE CURRENT REVISION: 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.316 2026/08/07 02:25:54 thorpej Exp $"); 62 63 #include "opt_ata.h" 64 #include "opt_wdc.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/conf.h> 70 #include <sys/buf.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 #include <sys/kmem.h> 74 #include <sys/syslog.h> 75 #include <sys/proc.h> 76 77 #include <sys/intr.h> 78 #include <sys/bus.h> 79 80 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 81 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 82 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 83 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 84 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 85 #define bus_space_read_stream_2 bus_space_read_2 86 #define bus_space_read_stream_4 bus_space_read_4 87 #define bus_space_write_stream_2 bus_space_write_2 88 #define bus_space_write_stream_4 bus_space_write_4 89 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 90 91 #include <dev/ata/atavar.h> 92 #include <dev/ata/atareg.h> 93 #include <dev/ata/satareg.h> 94 #include <dev/ata/satavar.h> 95 #include <dev/ic/wdcreg.h> 96 #include <dev/ic/wdcvar.h> 97 98 #include "locators.h" 99 100 #include "atapibus.h" 101 #include "wd.h" 102 #include "sata.h" 103 104 #define WDCDELAY 100 /* 100 microseconds */ 105 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 106 #if 0 107 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 108 #define WDCNDELAY_DEBUG 50 109 #endif 110 111 /* When polling wait that much and then kpause for 1/hz seconds */ 112 #define WDCDELAY_POLL 1 /* ms */ 113 114 /* timeout for the control commands */ 115 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 116 117 /* 118 * timeout when waiting for BSY to deassert when probing. 119 * set to 5s. From the standards this could be up to 31, but we can't 120 * wait that much at boot time, and 5s seems to be enough. 121 */ 122 #define WDC_PROBE_WAIT 5 123 124 125 #if NWD > 0 126 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 127 #else 128 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 129 const struct ata_bustype wdc_ata_bustype = { 130 .bustype_type = SCSIPI_BUSTYPE_ATA, 131 .ata_bio = NULL, 132 .ata_reset_drive = NULL, 133 .ata_reset_channel = wdc_reset_channel, 134 .ata_exec_command = wdc_exec_command, 135 .ata_get_params = NULL, 136 .ata_addref = NULL, 137 .ata_delref = NULL, 138 .ata_killpending = NULL, 139 .ata_recovery = NULL, 140 }; 141 #endif 142 143 /* Flags to wdcreset(). */ 144 #define RESET_POLL 1 145 #define RESET_SLEEP 0 /* wdcreset() will use kpause() */ 146 147 static int wdcprobe1(struct ata_channel *, int); 148 static int wdcreset(struct ata_channel *, int); 149 static void __wdcerror(struct ata_channel *, const char *); 150 static int __wdcwait_reset(struct ata_channel *, int, int); 151 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 152 static int __wdccommand_poll(struct ata_channel *, struct ata_xfer *); 153 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 154 static void __wdccommand_kill_xfer(struct ata_channel *, 155 struct ata_xfer *, int); 156 static int __wdccommand_start(struct ata_channel *, struct ata_xfer *); 157 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 158 static int __wdcwait(struct ata_channel *, int, int, int, int *); 159 160 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 161 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 162 #define DEBUG_INTR 0x01 163 #define DEBUG_XFERS 0x02 164 #define DEBUG_STATUS 0x04 165 #define DEBUG_FUNCS 0x08 166 #define DEBUG_PROBE 0x10 167 #define DEBUG_DETACH 0x20 168 #define DEBUG_DELAY 0x40 169 #ifdef ATADEBUG 170 extern int atadebug_mask; /* init'ed in ata.c */ 171 int wdc_nxfer = 0; 172 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 173 #else 174 #define ATADEBUG_PRINT(args, level) 175 #endif 176 177 /* 178 * Initialize the "shadow register" handles for a standard wdc controller. 179 */ 180 void 181 wdc_init_shadow_regs(struct wdc_regs *wdr) 182 { 183 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 184 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 185 } 186 187 /* 188 * Allocate a wdc_regs array, based on the number of channels. 189 */ 190 void 191 wdc_allocate_regs(struct wdc_softc *wdc) 192 { 193 194 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 195 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 196 } 197 198 #if NSATA > 0 199 /* 200 * probe drives on SATA controllers with standard SATA registers: 201 * bring the PHYs online, read the drive signature and set drive flags 202 * appropriately. 203 */ 204 void 205 wdc_sataprobe(struct ata_channel *chp) 206 { 207 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 208 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 209 uint8_t st = 0, sc __unused, sn __unused, cl, ch; 210 int i; 211 212 KASSERT(chp->ch_ndrives == 0 || chp->ch_drive != NULL); 213 214 /* do this before we take lock */ 215 216 ata_channel_lock(chp); 217 218 /* reset the PHY and bring online */ 219 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 220 wdr->sata_status, AT_WAIT)) { 221 case SStatus_DET_DEV: 222 /* wait 5s for BSY to clear */ 223 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 224 bus_space_write_1(wdr->cmd_iot, 225 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 226 delay(10); /* 400ns delay */ 227 st = bus_space_read_1(wdr->cmd_iot, 228 wdr->cmd_iohs[wd_status], 0); 229 if ((st & WDCS_BSY) == 0) 230 break; 231 ata_delay(chp, 1, "sataprb", AT_WAIT); 232 } 233 if (i == WDC_PROBE_WAIT * hz) 234 aprint_error_dev(chp->ch_atac->atac_dev, 235 "BSY never cleared, status 0x%02x\n", st); 236 sc = bus_space_read_1(wdr->cmd_iot, 237 wdr->cmd_iohs[wd_seccnt], 0); 238 sn = bus_space_read_1(wdr->cmd_iot, 239 wdr->cmd_iohs[wd_sector], 0); 240 cl = bus_space_read_1(wdr->cmd_iot, 241 wdr->cmd_iohs[wd_cyl_lo], 0); 242 ch = bus_space_read_1(wdr->cmd_iot, 243 wdr->cmd_iohs[wd_cyl_hi], 0); 244 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 245 "cl=0x%x ch=0x%x\n", 246 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 247 sc, sn, cl, ch), DEBUG_PROBE); 248 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) { 249 ata_channel_unlock(chp); 250 return; 251 } 252 /* 253 * sc and sn are supposed to be 0x1 for ATAPI, but in some 254 * cases we get wrong values here, so ignore it. 255 */ 256 if (cl == 0x14 && ch == 0xeb) 257 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; 258 else 259 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; 260 261 /* 262 * issue a reset in case only the interface part of the drive 263 * is up 264 */ 265 if (wdcreset(chp, RESET_SLEEP) != 0) 266 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 267 break; 268 269 default: 270 break; 271 } 272 273 ata_channel_unlock(chp); 274 } 275 #endif /* NSATA > 0 */ 276 277 278 /* Test to see controller with at last one attached drive is there. 279 * Returns a bit for each possible drive found (0x01 for drive 0, 280 * 0x02 for drive 1). 281 * Logic: 282 * - If a status register is at 0xff, assume there is no drive here 283 * (ISA has pull-up resistors). Similarly if the status register has 284 * the value we last wrote to the bus (for IDE interfaces without pullups). 285 * If no drive at all -> return. 286 * - reset the controller, wait for it to complete (may take up to 31s !). 287 * If timeout -> return. 288 * - test ATA/ATAPI signatures. If at last one drive found -> return. 289 * - try an ATA command on the master. 290 */ 291 292 void 293 wdc_drvprobe(struct ata_channel *chp) 294 { 295 struct ataparams params; /* XXX: large struct */ 296 struct atac_softc *atac = chp->ch_atac; 297 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 298 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 299 u_int8_t st0 = 0, st1 = 0; 300 int i, j, error, tfd; 301 302 ata_channel_lock(chp); 303 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) { 304 ata_channel_unlock(chp); 305 return; 306 } 307 if (wdcprobe1(chp, 0) == 0) { 308 /* No drives, abort the attach here. */ 309 atabus_free_drives(chp); 310 ata_channel_unlock(chp); 311 return; 312 } 313 314 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 315 for (i = 0; i < mstohz(3000); i++) { 316 /* 317 * select drive 1 first, so that master is selected on 318 * exit from the loop 319 */ 320 if (chp->ch_ndrives > 1 && 321 chp->ch_drive[1].drive_type == ATA_DRIVET_ATA) { 322 if (wdc->select) 323 wdc->select(chp,1); 324 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 325 0, WDSD_IBM | 0x10); 326 delay(10); /* 400ns delay */ 327 st1 = bus_space_read_1(wdr->cmd_iot, 328 wdr->cmd_iohs[wd_status], 0); 329 } 330 if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATA) { 331 if (wdc->select) 332 wdc->select(chp,0); 333 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 334 0, WDSD_IBM); 335 delay(10); /* 400ns delay */ 336 st0 = bus_space_read_1(wdr->cmd_iot, 337 wdr->cmd_iohs[wd_status], 0); 338 } 339 340 341 if ((chp->ch_drive[0].drive_type != ATA_DRIVET_ATA || 342 (st0 & WDCS_DRDY)) && 343 (chp->ch_ndrives < 2 || 344 chp->ch_drive[1].drive_type != ATA_DRIVET_ATA || 345 (st1 & WDCS_DRDY))) 346 break; 347 #ifdef WDC_NO_IDS 348 /* cannot kpause here (can't enable IPL_BIO interrupts), 349 * delay instead 350 */ 351 delay(1000000 / hz); 352 #else 353 ata_delay(chp, 1, "atadrdy", AT_WAIT); 354 #endif 355 } 356 if ((st0 & WDCS_DRDY) == 0 && 357 chp->ch_drive[0].drive_type != ATA_DRIVET_ATAPI) 358 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 359 if (chp->ch_ndrives > 1 && (st1 & WDCS_DRDY) == 0 && 360 chp->ch_drive[1].drive_type != ATA_DRIVET_ATAPI) 361 chp->ch_drive[1].drive_type = ATA_DRIVET_NONE; 362 ata_channel_unlock(chp); 363 364 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 365 device_xname(atac->atac_dev), 366 chp->ch_channel, st0, st1), DEBUG_PROBE); 367 368 /* Wait a bit, some devices are weird just after a reset. */ 369 delay(5000); 370 371 for (i = 0; i < chp->ch_ndrives; i++) { 372 #if NATA_DMA 373 /* 374 * Init error counter so that an error within the first xfers 375 * will trigger a downgrade 376 */ 377 chp->ch_drive[i].n_dmaerrs = NERRS_MAX - 1; 378 #endif 379 380 switch (atac->atac_cap & (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) { 381 case 0: 382 /* 383 * Controller can only do 8-bit PIO; we will have 384 * to issue a SET_FEATURES to put the drive into 385 * that mode. If it fails, we will ignore the 386 * drive. 387 */ 388 aprint_verbose("%s:%d:%d: setting PIO8_EN\n", 389 device_xname(atac->atac_dev), 390 chp->ch_channel, i); 391 error = ata_set_pio8(&chp->ch_drive[i], 392 AT_WAIT | AT_POLL); 393 if (error != CMD_OK) { 394 aprint_error("%s:%d:%d: failed to set " 395 "8-bit PIO (%d)\n", 396 device_xname(atac->atac_dev), 397 chp->ch_channel, i, error); 398 ata_channel_lock(chp); 399 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 400 ata_channel_unlock(chp); 401 } 402 break; 403 404 case ATAC_CAP_DATA32: 405 /* 406 * If the controller can't do 16-bit, then flag 407 * the drives as 32-bit. 408 */ 409 ata_channel_lock(chp); 410 chp->ch_drive[i].drive_flags |= ATA_DRIVE_CAP32; 411 ata_channel_unlock(chp); 412 break; 413 414 default: 415 break; 416 } 417 418 if (chp->ch_drive[i].drive_type == ATA_DRIVET_NONE) 419 continue; 420 421 /* Shortcut in case we've been shutdown */ 422 if (chp->ch_flags & ATACH_SHUTDOWN) 423 return; 424 425 /* 426 * Issue an identify, to try to detect ghosts. 427 * Note that we can't use interrupts here, because if there 428 * is no devices, we will get a command aborted without 429 * interrupts. 430 */ 431 error = ata_get_params(&chp->ch_drive[i], 432 AT_WAIT | AT_POLL, ¶ms); 433 if (error != CMD_OK) { 434 ata_channel_lock(chp); 435 ata_delay(chp, 1000, "atacnf", AT_WAIT); 436 ata_channel_unlock(chp); 437 438 /* Shortcut in case we've been shutdown */ 439 if (chp->ch_flags & ATACH_SHUTDOWN) 440 return; 441 442 error = ata_get_params(&chp->ch_drive[i], 443 AT_WAIT | AT_POLL, ¶ms); 444 } 445 if (error != CMD_OK) { 446 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 447 device_xname(atac->atac_dev), 448 chp->ch_channel, i, error), DEBUG_PROBE); 449 ata_channel_lock(chp); 450 if (chp->ch_drive[i].drive_type != ATA_DRIVET_ATA || 451 (wdc->cap & WDC_CAPABILITY_PREATA) == 0) { 452 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 453 ata_channel_unlock(chp); 454 continue; 455 } 456 /* 457 * Pre-ATA drive ? 458 * Test registers writability (Error register not 459 * writable, but cyllo is), then try an ATA command. 460 */ 461 if (wdc->select) 462 wdc->select(chp,i); 463 bus_space_write_1(wdr->cmd_iot, 464 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 465 delay(10); /* 400ns delay */ 466 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 467 0, 0x58); 468 bus_space_write_1(wdr->cmd_iot, 469 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 470 if (bus_space_read_1(wdr->cmd_iot, 471 wdr->cmd_iohs[wd_error], 0) == 0x58 || 472 bus_space_read_1(wdr->cmd_iot, 473 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 474 ATADEBUG_PRINT(("%s:%d:%d: register " 475 "writability failed\n", 476 device_xname(atac->atac_dev), 477 chp->ch_channel, i), DEBUG_PROBE); 478 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 479 ata_channel_unlock(chp); 480 continue; 481 } 482 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 483 WDCWAIT_TOUT) { 484 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 485 device_xname(atac->atac_dev), 486 chp->ch_channel, i), DEBUG_PROBE); 487 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 488 ata_channel_unlock(chp); 489 continue; 490 } 491 bus_space_write_1(wdr->cmd_iot, 492 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 493 delay(10); /* 400ns delay */ 494 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 495 WDCWAIT_TOUT) { 496 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 497 device_xname(atac->atac_dev), 498 chp->ch_channel, i), DEBUG_PROBE); 499 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 500 ata_channel_unlock(chp); 501 } else { 502 for (j = 0; j < chp->ch_ndrives; j++) { 503 if (chp->ch_drive[i].drive_type != 504 ATA_DRIVET_NONE) { 505 chp->ch_drive[j].drive_type = 506 ATA_DRIVET_OLD; 507 } 508 } 509 ata_channel_unlock(chp); 510 } 511 } 512 } 513 } 514 515 int 516 wdcprobe(struct wdc_regs *wdr) 517 { 518 519 return wdcprobe_with_reset(wdr, NULL); 520 } 521 522 int 523 wdcprobe_with_reset(struct wdc_regs *wdr, 524 void (*do_reset)(struct ata_channel *, int)) 525 { 526 struct wdc_softc *wdc; 527 struct ata_channel *ch; 528 int rv; 529 530 wdc = kmem_zalloc(sizeof(*wdc), KM_SLEEP); 531 ch = kmem_zalloc(sizeof(*ch), KM_SLEEP); 532 533 ata_channel_init(ch); 534 ch->ch_atac = &wdc->sc_atac; 535 wdc->regs = wdr; 536 537 /* check the MD reset method */ 538 wdc->reset = (do_reset != NULL) ? do_reset : wdc_do_reset; 539 540 ata_channel_lock(ch); 541 rv = wdcprobe1(ch, 1); 542 ata_channel_unlock(ch); 543 544 ata_channel_destroy(ch); 545 546 kmem_free(ch, sizeof(*ch)); 547 kmem_free(wdc, sizeof(*wdc)); 548 549 return rv; 550 } 551 552 static int 553 wdcprobe1(struct ata_channel *chp, int poll) 554 { 555 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 556 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 557 u_int8_t st0 = 0, st1 = 0, sc __unused, sn __unused, cl, ch; 558 u_int8_t ret_value = 0x03; 559 u_int8_t drive; 560 /* XXX if poll, wdc_probe_count is 0. */ 561 int wdc_probe_count = 562 poll ? (WDC_PROBE_WAIT / WDCDELAY) 563 : (WDC_PROBE_WAIT * hz); 564 565 /* 566 * Sanity check to see if the wdc channel responds at all. 567 */ 568 569 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 570 while (wdc_probe_count-- > 0) { 571 if (wdc->select) 572 wdc->select(chp,0); 573 574 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 575 0, WDSD_IBM); 576 delay(10); /* 400ns delay */ 577 st0 = bus_space_read_1(wdr->cmd_iot, 578 wdr->cmd_iohs[wd_status], 0); 579 580 if (wdc->select) 581 wdc->select(chp,1); 582 583 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 584 0, WDSD_IBM | 0x10); 585 delay(10); /* 400ns delay */ 586 st1 = bus_space_read_1(wdr->cmd_iot, 587 wdr->cmd_iohs[wd_status], 0); 588 if ((st0 & WDCS_BSY) == 0) 589 break; 590 } 591 592 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 593 __func__, chp->ch_channel, st0, st1), DEBUG_PROBE); 594 595 /* 596 * Is a drive present? Originally this code tested either 597 * for 0xff (ISA controller with no drive present; pull-ups 598 * take reg values high) or "echo", which meant writing to 599 * the notionally read-only geometry regs and seeing if we 600 * could read back what we wrote (if a drive is there, we 601 * will not). But some PCI controllers don't have the 602 * 0xff behavior and also share regs internally in a way 603 * that tricks the echo test, resulting in a 3 second delay 604 * later before we find no drive. We conditionally check for 605 * 0x00 which should catch this case because a drive that's 606 * actually present should have at least BSY or DRDY set. 607 */ 608 if (st0 == 0xff || st0 == WDSD_IBM) 609 ret_value &= ~0x01; 610 else if (st0 == 0x00 && 611 (wdc->cap & WDC_CAPABILITY_ZERO_ABSENT)) 612 ret_value &= ~0x01; 613 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 614 ret_value &= ~0x02; 615 else if (st0 == 0x00 && 616 (wdc->cap & WDC_CAPABILITY_ZERO_ABSENT)) 617 ret_value &= ~0x02; 618 /* Register writability test, drive 0. */ 619 if (ret_value & 0x01) { 620 if (wdc->select) 621 wdc->select(chp,0); 622 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 623 0, WDSD_IBM); 624 bus_space_write_1(wdr->cmd_iot, 625 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 626 cl = bus_space_read_1(wdr->cmd_iot, 627 wdr->cmd_iohs[wd_cyl_lo], 0); 628 if (cl != 0x02) { 629 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 630 "got 0x%x != 0x02\n", 631 __func__, chp->ch_channel, cl), 632 DEBUG_PROBE); 633 ret_value &= ~0x01; 634 } 635 bus_space_write_1(wdr->cmd_iot, 636 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 637 cl = bus_space_read_1(wdr->cmd_iot, 638 wdr->cmd_iohs[wd_cyl_lo], 0); 639 if (cl != 0x01) { 640 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 641 "got 0x%x != 0x01\n", 642 __func__, chp->ch_channel, cl), 643 DEBUG_PROBE); 644 ret_value &= ~0x01; 645 } 646 bus_space_write_1(wdr->cmd_iot, 647 wdr->cmd_iohs[wd_sector], 0, 0x01); 648 cl = bus_space_read_1(wdr->cmd_iot, 649 wdr->cmd_iohs[wd_sector], 0); 650 if (cl != 0x01) { 651 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 652 "got 0x%x != 0x01\n", 653 __func__, chp->ch_channel, cl), 654 DEBUG_PROBE); 655 ret_value &= ~0x01; 656 } 657 bus_space_write_1(wdr->cmd_iot, 658 wdr->cmd_iohs[wd_sector], 0, 0x02); 659 cl = bus_space_read_1(wdr->cmd_iot, 660 wdr->cmd_iohs[wd_sector], 0); 661 if (cl != 0x02) { 662 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 663 "got 0x%x != 0x02\n", 664 __func__, chp->ch_channel, cl), 665 DEBUG_PROBE); 666 ret_value &= ~0x01; 667 } 668 cl = bus_space_read_1(wdr->cmd_iot, 669 wdr->cmd_iohs[wd_cyl_lo], 0); 670 if (cl != 0x01) { 671 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 672 "got 0x%x != 0x01\n", 673 __func__, chp->ch_channel, cl), 674 DEBUG_PROBE); 675 ret_value &= ~0x01; 676 } 677 } 678 /* Register writability test, drive 1. */ 679 if (ret_value & 0x02) { 680 if (wdc->select) 681 wdc->select(chp,1); 682 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 683 0, WDSD_IBM | 0x10); 684 bus_space_write_1(wdr->cmd_iot, 685 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 686 cl = bus_space_read_1(wdr->cmd_iot, 687 wdr->cmd_iohs[wd_cyl_lo], 0); 688 if (cl != 0x02) { 689 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 690 "got 0x%x != 0x02\n", 691 __func__, chp->ch_channel, cl), 692 DEBUG_PROBE); 693 ret_value &= ~0x02; 694 } 695 bus_space_write_1(wdr->cmd_iot, 696 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 697 cl = bus_space_read_1(wdr->cmd_iot, 698 wdr->cmd_iohs[wd_cyl_lo], 0); 699 if (cl != 0x01) { 700 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 701 "got 0x%x != 0x01\n", 702 __func__, chp->ch_channel, cl), 703 DEBUG_PROBE); 704 ret_value &= ~0x02; 705 } 706 bus_space_write_1(wdr->cmd_iot, 707 wdr->cmd_iohs[wd_sector], 0, 0x01); 708 cl = bus_space_read_1(wdr->cmd_iot, 709 wdr->cmd_iohs[wd_sector], 0); 710 if (cl != 0x01) { 711 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 712 "got 0x%x != 0x01\n", 713 __func__, chp->ch_channel, cl), 714 DEBUG_PROBE); 715 ret_value &= ~0x02; 716 } 717 bus_space_write_1(wdr->cmd_iot, 718 wdr->cmd_iohs[wd_sector], 0, 0x02); 719 cl = bus_space_read_1(wdr->cmd_iot, 720 wdr->cmd_iohs[wd_sector], 0); 721 if (cl != 0x02) { 722 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 723 "got 0x%x != 0x02\n", 724 __func__, chp->ch_channel, cl), 725 DEBUG_PROBE); 726 ret_value &= ~0x02; 727 } 728 cl = bus_space_read_1(wdr->cmd_iot, 729 wdr->cmd_iohs[wd_cyl_lo], 0); 730 if (cl != 0x01) { 731 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 732 "got 0x%x != 0x01\n", 733 __func__, chp->ch_channel, cl), 734 DEBUG_PROBE); 735 ret_value &= ~0x02; 736 } 737 } 738 739 if (ret_value == 0) { 740 return 0; 741 } 742 } 743 744 #if 0 /* XXX this break some ATA or ATAPI devices */ 745 /* 746 * reset bus. Also send an ATAPI_RESET to devices, in case there are 747 * ATAPI device out there which don't react to the bus reset 748 */ 749 if (ret_value & 0x01) { 750 if (wdc->select) 751 wdc->select(chp,0); 752 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 753 0, WDSD_IBM); 754 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 755 ATAPI_SOFT_RESET); 756 } 757 if (ret_value & 0x02) { 758 if (wdc->select) 759 wdc->select(chp,0); 760 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 761 0, WDSD_IBM | 0x10); 762 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 763 ATAPI_SOFT_RESET); 764 } 765 766 delay(5000); 767 #endif 768 769 wdc->reset(chp, RESET_POLL); 770 DELAY(2000); 771 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 772 773 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 774 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 775 WDCTL_4BIT); 776 777 #ifdef WDC_NO_IDS 778 ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); 779 #else 780 ret_value = __wdcwait_reset(chp, ret_value, poll); 781 #endif 782 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=%#x\n", 783 __func__, chp->ch_channel, ret_value), DEBUG_PROBE); 784 785 /* if reset failed, there's nothing here */ 786 if (ret_value == 0) { 787 return 0; 788 } 789 790 /* 791 * Test presence of drives. First test register signatures looking 792 * for ATAPI devices. If it's not an ATAPI and reset said there may 793 * be something here assume it's ATA or OLD. Ghost will be killed 794 * later in attach routine. 795 */ 796 for (drive = 0; drive < wdc->wdc_maxdrives; drive++) { 797 if ((ret_value & (0x01 << drive)) == 0) 798 continue; 799 if (wdc->select) 800 wdc->select(chp,drive); 801 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 802 WDSD_IBM | (drive << 4)); 803 delay(10); /* 400ns delay */ 804 /* Save registers contents */ 805 sc = bus_space_read_1(wdr->cmd_iot, 806 wdr->cmd_iohs[wd_seccnt], 0); 807 sn = bus_space_read_1(wdr->cmd_iot, 808 wdr->cmd_iohs[wd_sector], 0); 809 cl = bus_space_read_1(wdr->cmd_iot, 810 wdr->cmd_iohs[wd_cyl_lo], 0); 811 ch = bus_space_read_1(wdr->cmd_iot, 812 wdr->cmd_iohs[wd_cyl_hi], 0); 813 814 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 815 "cl=0x%x ch=0x%x\n", __func__, chp->ch_channel, drive, sc, 816 sn, cl, ch), DEBUG_PROBE); 817 /* 818 * sc & sn are supposed to be 0x1 for ATAPI but in some cases 819 * we get wrong values here, so ignore it. 820 */ 821 if (chp->ch_drive != NULL) { 822 if (cl == 0x14 && ch == 0xeb) { 823 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATAPI; 824 } else { 825 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATA; 826 } 827 } 828 } 829 /* 830 * Select an existing drive before lowering spl, some WDC_NO_IDS 831 * devices incorrectly assert IRQ on nonexistent slave 832 */ 833 if (ret_value & 0x01) { 834 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 835 WDSD_IBM); 836 (void)bus_space_read_1(wdr->cmd_iot, 837 wdr->cmd_iohs[wd_status], 0); 838 } 839 return (ret_value); 840 } 841 842 void 843 wdcattach(struct ata_channel *chp) 844 { 845 struct atac_softc *atac = chp->ch_atac; 846 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 847 848 KASSERT(wdc->wdc_maxdrives > 0 && wdc->wdc_maxdrives <= WDC_MAXDRIVES); 849 850 /* default data transfer methods */ 851 if (wdc->datain_pio == NULL) 852 wdc->datain_pio = wdc_datain_pio; 853 if (wdc->dataout_pio == NULL) 854 wdc->dataout_pio = wdc_dataout_pio; 855 /* default reset method */ 856 if (wdc->reset == NULL) 857 wdc->reset = wdc_do_reset; 858 859 /* initialise global data */ 860 if (atac->atac_bustype_ata == NULL) 861 atac->atac_bustype_ata = &wdc_ata_bustype; 862 if (atac->atac_probe == NULL) 863 atac->atac_probe = wdc_drvprobe; 864 #if NATAPIBUS > 0 865 if (atac->atac_atapibus_attach == NULL) 866 atac->atac_atapibus_attach = wdc_atapibus_attach; 867 #endif 868 869 ata_channel_attach(chp); 870 } 871 872 void 873 wdc_childdetached(device_t self, device_t child) 874 { 875 struct atac_softc *atac = device_private(self); 876 struct ata_channel *chp; 877 int i; 878 879 for (i = 0; i < atac->atac_nchannels; i++) { 880 chp = atac->atac_channels[i]; 881 if (child == chp->atabus) { 882 chp->atabus = NULL; 883 return; 884 } 885 } 886 } 887 888 int 889 wdcdetach(device_t self, int flags) 890 { 891 struct atac_softc *atac = device_private(self); 892 struct ata_channel *chp; 893 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 894 int i, error = 0; 895 896 for (i = 0; i < atac->atac_nchannels; i++) { 897 chp = atac->atac_channels[i]; 898 if (chp->atabus == NULL) 899 continue; 900 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 901 device_xname(atac->atac_dev), device_xname(chp->atabus)), 902 DEBUG_DETACH); 903 if ((error = config_detach(chp->atabus, flags)) != 0) 904 return error; 905 ata_channel_detach(chp); 906 } 907 if (adapt->adapt_refcnt != 0) 908 return EBUSY; 909 return 0; 910 } 911 912 /* restart an interrupted I/O */ 913 void 914 wdcrestart(void *v) 915 { 916 struct ata_channel *chp = v; 917 int s; 918 919 s = splbio(); 920 atastart(chp); 921 splx(s); 922 } 923 924 925 /* 926 * Interrupt routine for the controller. Acknowledge the interrupt, check for 927 * errors on the current operation, mark it done if necessary, and start the 928 * next request. Also check for a partially done transfer, and continue with 929 * the next chunk if so. 930 */ 931 int 932 wdcintr(void *arg) 933 { 934 struct ata_channel *chp = arg; 935 struct atac_softc *atac = chp->ch_atac; 936 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 937 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 938 struct ata_xfer *xfer; 939 int ret; 940 941 if (!device_is_active(atac->atac_dev)) { 942 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 943 DEBUG_INTR); 944 return (0); 945 } 946 947 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) 948 goto ignore; 949 950 xfer = ata_queue_get_active_xfer(chp); 951 if (xfer == NULL) { 952 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 953 ignore: 954 /* try to clear the pending interrupt anyway */ 955 (void)bus_space_read_1(wdr->cmd_iot, 956 wdr->cmd_iohs[wd_status], 0); 957 return (0); 958 } 959 960 /* 961 * On some controllers (e.g. some PCI-IDE) setting the WDCTL_IDS bit 962 * actually has no effect, and interrupt is triggered regardless. 963 * Ignore polled commands here, they are processed separately. 964 */ 965 if (ISSET(xfer->c_flags, C_POLL)) { 966 ATADEBUG_PRINT(("%s: polled xfer ignored\n", __func__), 967 DEBUG_INTR); 968 goto ignore; 969 } 970 971 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 972 KASSERT(xfer != NULL); 973 974 #if NATA_DMA || NATA_PIOBM 975 if (chp->ch_flags & ATACH_DMA_WAIT) { 976 wdc->dma_status = 977 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 978 xfer->c_drive, WDC_DMAEND_END); 979 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 980 /* IRQ not for us, not detected by DMA engine */ 981 return 0; 982 } 983 chp->ch_flags &= ~ATACH_DMA_WAIT; 984 } 985 #endif 986 chp->ch_flags &= ~ATACH_IRQ_WAIT; 987 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 988 ret = xfer->ops->c_intr(chp, xfer, 1); 989 if (ret == 0) /* irq was not for us, still waiting for irq */ 990 chp->ch_flags |= ATACH_IRQ_WAIT; 991 return (ret); 992 } 993 994 /* Put all disk in RESET state */ 995 void 996 wdc_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 997 { 998 struct ata_channel *chp = drvp->chnl_softc; 999 1000 ata_channel_lock_owned(chp); 1001 1002 KASSERT(sigp == NULL); 1003 1004 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 1005 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1006 drvp->drive), DEBUG_FUNCS); 1007 1008 ata_thread_run(chp, flags, ATACH_TH_RESET, ATACH_NODRIVE); 1009 } 1010 1011 void 1012 wdc_reset_channel(struct ata_channel *chp, int flags) 1013 { 1014 struct ata_xfer *xfer; 1015 1016 ata_channel_lock_owned(chp); 1017 1018 #if NATA_DMA || NATA_PIOBM 1019 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1020 #endif 1021 1022 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1023 1024 /* 1025 * if the current command is on an ATAPI device, issue a 1026 * ATAPI_SOFT_RESET 1027 */ 1028 xfer = ata_queue_get_active_xfer_locked(chp); 1029 1030 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 1031 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 1032 ata_delay(chp, 1000, "atardl", flags); 1033 } 1034 1035 /* reset the channel */ 1036 if (flags & AT_WAIT) 1037 (void) wdcreset(chp, RESET_SLEEP); 1038 else 1039 (void) wdcreset(chp, RESET_POLL); 1040 1041 /* 1042 * wait a bit after reset; in case the DMA engines needs some time 1043 * to recover. 1044 */ 1045 ata_delay(chp, 1000, "atardl", flags); 1046 1047 /* 1048 * Look for pending xfers. If we have a shared queue, we'll also reset 1049 * the other channel if the current xfer is running on it. 1050 * Then we'll kill the eventual active transfer explicitly, so that 1051 * it is queued for retry immediately without waiting for I/O timeout. 1052 */ 1053 if (xfer) { 1054 if (xfer->c_chp != chp) { 1055 ata_thread_run(xfer->c_chp, flags, ATACH_TH_RESET, 1056 ATACH_NODRIVE); 1057 } else { 1058 #if NATA_DMA || NATA_PIOBM 1059 /* 1060 * If we're waiting for DMA, stop the 1061 * DMA engine 1062 */ 1063 if (chp->ch_flags & ATACH_DMA_WAIT) { 1064 (*wdc->dma_finish)(wdc->dma_arg, 1065 chp->ch_channel, xfer->c_drive, 1066 WDC_DMAEND_ABRT_QUIET); 1067 chp->ch_flags &= ~ATACH_DMA_WAIT; 1068 } 1069 #endif 1070 } 1071 } 1072 1073 ata_kill_active(chp, KILL_RESET, flags); 1074 } 1075 1076 static int 1077 wdcreset(struct ata_channel *chp, int poll) 1078 { 1079 struct atac_softc *atac = chp->ch_atac; 1080 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1081 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1082 int drv_mask1 = 0, drv_mask2; 1083 1084 ata_channel_lock_owned(chp); 1085 1086 #ifdef WDC_NO_IDS 1087 poll = RESET_POLL; 1088 #endif 1089 wdc->reset(chp, poll); 1090 1091 if (chp->ch_ndrives > 0) 1092 drv_mask1 = (chp->ch_drive[0].drive_type != ATA_DRIVET_NONE) 1093 ? 0x01 : 0x00; 1094 if (chp->ch_ndrives > 1) 1095 drv_mask1 |= (chp->ch_drive[1].drive_type != ATA_DRIVET_NONE) 1096 ? 0x02 : 0x00; 1097 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1098 (poll == RESET_SLEEP) ? 0 : 1); 1099 if (drv_mask2 != drv_mask1) { 1100 aprint_error("%s channel %d: reset failed for", 1101 device_xname(atac->atac_dev), chp->ch_channel); 1102 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1103 aprint_normal(" drive 0"); 1104 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1105 aprint_normal(" drive 1"); 1106 aprint_normal("\n"); 1107 } 1108 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1109 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1110 WDCTL_4BIT); 1111 1112 return (drv_mask1 != drv_mask2) ? 1 : 0; 1113 } 1114 1115 void 1116 wdc_do_reset(struct ata_channel *chp, int poll) 1117 { 1118 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1119 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1120 int s = 0; 1121 1122 if (poll != RESET_SLEEP) 1123 s = splbio(); 1124 if (wdc->select) 1125 wdc->select(chp,0); 1126 /* master */ 1127 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1128 delay(10); /* 400ns delay */ 1129 /* assert SRST, wait for reset to complete */ 1130 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1131 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1132 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1133 delay(2000); 1134 } 1135 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1136 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1137 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1138 WDCTL_4BIT | WDCTL_IDS); 1139 delay(10); /* 400ns delay */ 1140 if (poll != RESET_SLEEP) { 1141 /* ACK interrupt in case there is one pending left */ 1142 if (wdc->irqack) 1143 wdc->irqack(chp); 1144 splx(s); 1145 } 1146 } 1147 1148 static int 1149 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1150 { 1151 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1152 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1153 int timeout, nloop; 1154 int wflags = poll ? AT_POLL : AT_WAIT; 1155 u_int8_t st0 = 0, st1 = 0; 1156 #ifdef ATADEBUG 1157 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1158 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1159 #endif 1160 if (poll) 1161 nloop = WDCNDELAY_RST; 1162 else 1163 nloop = WDC_RESET_WAIT * hz / 1000; 1164 /* wait for BSY to deassert */ 1165 for (timeout = 0; timeout < nloop; timeout++) { 1166 if ((drv_mask & 0x01) != 0) { 1167 if (wdc->select) 1168 wdc->select(chp,0); 1169 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1170 0, WDSD_IBM); /* master */ 1171 delay(10); 1172 st0 = bus_space_read_1(wdr->cmd_iot, 1173 wdr->cmd_iohs[wd_status], 0); 1174 #ifdef ATADEBUG 1175 sc0 = bus_space_read_1(wdr->cmd_iot, 1176 wdr->cmd_iohs[wd_seccnt], 0); 1177 sn0 = bus_space_read_1(wdr->cmd_iot, 1178 wdr->cmd_iohs[wd_sector], 0); 1179 cl0 = bus_space_read_1(wdr->cmd_iot, 1180 wdr->cmd_iohs[wd_cyl_lo], 0); 1181 ch0 = bus_space_read_1(wdr->cmd_iot, 1182 wdr->cmd_iohs[wd_cyl_hi], 0); 1183 #endif 1184 } 1185 if ((drv_mask & 0x02) != 0) { 1186 if (wdc->select) 1187 wdc->select(chp,1); 1188 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1189 0, WDSD_IBM | 0x10); /* slave */ 1190 delay(10); 1191 st1 = bus_space_read_1(wdr->cmd_iot, 1192 wdr->cmd_iohs[wd_status], 0); 1193 #ifdef ATADEBUG 1194 sc1 = bus_space_read_1(wdr->cmd_iot, 1195 wdr->cmd_iohs[wd_seccnt], 0); 1196 sn1 = bus_space_read_1(wdr->cmd_iot, 1197 wdr->cmd_iohs[wd_sector], 0); 1198 cl1 = bus_space_read_1(wdr->cmd_iot, 1199 wdr->cmd_iohs[wd_cyl_lo], 0); 1200 ch1 = bus_space_read_1(wdr->cmd_iot, 1201 wdr->cmd_iohs[wd_cyl_hi], 0); 1202 #endif 1203 } 1204 1205 if ((drv_mask & 0x01) == 0) { 1206 /* no master */ 1207 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1208 /* No master, slave is ready, it's done */ 1209 goto end; 1210 } 1211 if ((drv_mask & 0x02) == 0) { 1212 /* No master, no slave: it's done */ 1213 goto end; 1214 } 1215 } else if ((drv_mask & 0x02) == 0) { 1216 /* no slave */ 1217 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1218 /* No slave, master is ready, it's done */ 1219 goto end; 1220 } 1221 } else { 1222 /* Wait for both master and slave to be ready */ 1223 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1224 goto end; 1225 } 1226 } 1227 ata_delay(chp, WDCDELAY, "atarst", wflags); 1228 } 1229 /* Reset timed out. Maybe it's because drv_mask was not right */ 1230 if (st0 & WDCS_BSY) 1231 drv_mask &= ~0x01; 1232 if (st1 & WDCS_BSY) 1233 drv_mask &= ~0x02; 1234 end: 1235 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1236 "cl=0x%x ch=0x%x\n", 1237 device_xname(chp->ch_atac->atac_dev), 1238 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1239 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1240 "cl=0x%x ch=0x%x\n", 1241 device_xname(chp->ch_atac->atac_dev), 1242 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1243 1244 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1245 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1246 st0, st1), DEBUG_PROBE); 1247 1248 return drv_mask; 1249 } 1250 1251 /* 1252 * Wait for a drive to be !BSY, and have mask in its status register. 1253 * return -1 for a timeout after "timeout" ms. 1254 */ 1255 static int 1256 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int *tfd) 1257 { 1258 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1259 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1260 u_char status, error = 0; 1261 int xtime = 0; 1262 int rv; 1263 1264 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1265 device_xname(chp->ch_atac->atac_dev), 1266 chp->ch_channel), DEBUG_STATUS); 1267 *tfd = 0; 1268 1269 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1270 1271 for (;;) { 1272 status = 1273 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1274 if ((status & (WDCS_BSY | mask)) == bits) 1275 break; 1276 if (++xtime > timeout) { 1277 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1278 "status %x error %x (mask 0x%x bits 0x%x)\n", 1279 xtime, status, 1280 bus_space_read_1(wdr->cmd_iot, 1281 wdr->cmd_iohs[wd_error], 0), mask, bits), 1282 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1283 rv = WDCWAIT_TOUT; 1284 goto out; 1285 } 1286 delay(WDCDELAY); 1287 } 1288 #ifdef ATADEBUG 1289 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1290 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1291 #endif 1292 if (status & WDCS_ERR) 1293 error = bus_space_read_1(wdr->cmd_iot, 1294 wdr->cmd_iohs[wd_error], 0); 1295 #ifdef WDCNDELAY_DEBUG 1296 /* After autoconfig, there should be no long delays. */ 1297 if (!cold && xtime > WDCNDELAY_DEBUG) { 1298 struct ata_xfer *xfer; 1299 1300 xfer = ata_queue_get_active_xfer_locked(chp); 1301 if (xfer == NULL) 1302 printf("%s channel %d: warning: busy-wait took %dus\n", 1303 device_xname(chp->ch_atac->atac_dev), 1304 chp->ch_channel, WDCDELAY * xtime); 1305 else 1306 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1307 device_xname(chp->ch_atac->atac_dev), 1308 chp->ch_channel, xfer->c_drive, 1309 WDCDELAY * xtime); 1310 } 1311 #endif 1312 rv = WDCWAIT_OK; 1313 1314 out: 1315 *tfd = ATACH_ERR_ST(error, status); 1316 return rv; 1317 } 1318 1319 /* 1320 * Call __wdcwait(), polling using kpause() or waking up the kernel 1321 * thread if possible 1322 */ 1323 int 1324 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags, 1325 int *tfd) 1326 { 1327 int error, i, timeout_hz = mstohz(timeout); 1328 1329 ata_channel_lock_owned(chp); 1330 1331 if (timeout_hz == 0 || 1332 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1333 error = __wdcwait(chp, mask, bits, timeout, tfd); 1334 else { 1335 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL, tfd); 1336 if (error != 0) { 1337 if (ata_is_thread_run(chp) || (flags & AT_WAIT)) { 1338 /* 1339 * we're running in the channel thread 1340 * or some userland thread context 1341 */ 1342 for (i = 0; i < timeout_hz; i++) { 1343 if (__wdcwait(chp, mask, bits, 1344 WDCDELAY_POLL, tfd) == 0) { 1345 error = 0; 1346 break; 1347 } 1348 kpause("atapoll", true, 1, 1349 &chp->ch_lock); 1350 } 1351 } else { 1352 /* 1353 * we're probably in interrupt context, 1354 * caller must ask the thread to come back here 1355 */ 1356 return(WDCWAIT_THR); 1357 } 1358 } 1359 } 1360 return (error); 1361 } 1362 1363 1364 #if NATA_DMA 1365 /* 1366 * Busy-wait for DMA to complete 1367 */ 1368 int 1369 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1370 { 1371 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1372 int xtime; 1373 1374 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1375 wdc->dma_status = 1376 (*wdc->dma_finish)(wdc->dma_arg, 1377 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1378 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1379 return 0; 1380 delay(WDCDELAY); 1381 } 1382 /* timeout, force a DMA halt */ 1383 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1384 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1385 return 1; 1386 } 1387 #endif 1388 1389 void 1390 wdctimeout(void *arg) 1391 { 1392 struct ata_xfer *xfer; 1393 struct ata_channel *chp = arg; 1394 #if NATA_DMA || NATA_PIOBM 1395 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1396 #endif 1397 int s; 1398 1399 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1400 1401 s = splbio(); 1402 1403 callout_ack(&chp->c_timo_callout); 1404 1405 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 1406 __wdcerror(chp, "timeout not expected without pending irq"); 1407 goto out; 1408 } 1409 1410 xfer = ata_queue_get_active_xfer(chp); 1411 KASSERT(xfer != NULL); 1412 1413 if (ata_timo_xfer_check(xfer)) { 1414 /* Already logged */ 1415 goto out; 1416 } 1417 1418 __wdcerror(chp, "lost interrupt"); 1419 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1420 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1421 xfer->c_bcount, xfer->c_skip); 1422 #if NATA_DMA || NATA_PIOBM 1423 if (chp->ch_flags & ATACH_DMA_WAIT) { 1424 wdc->dma_status = 1425 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 1426 xfer->c_drive, WDC_DMAEND_ABRT); 1427 chp->ch_flags &= ~ATACH_DMA_WAIT; 1428 } 1429 #endif 1430 /* 1431 * Call the interrupt routine. If we just missed an interrupt, 1432 * it will do what's needed. Else, it will take the needed 1433 * action (reset the device). 1434 */ 1435 xfer->c_flags |= C_TIMEOU; 1436 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1437 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 1438 xfer->ops->c_intr(chp, xfer, 1); 1439 1440 out: 1441 splx(s); 1442 } 1443 1444 static const struct ata_xfer_ops wdc_cmd_xfer_ops = { 1445 .c_start = __wdccommand_start, 1446 .c_poll = __wdccommand_poll, 1447 .c_abort = __wdccommand_done, 1448 .c_intr = __wdccommand_intr, 1449 .c_kill_xfer = __wdccommand_kill_xfer, 1450 }; 1451 1452 void 1453 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1454 { 1455 struct ata_channel *chp = drvp->chnl_softc; 1456 struct ata_command *ata_c = &xfer->c_ata_c; 1457 1458 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1459 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1460 drvp->drive), DEBUG_FUNCS); 1461 1462 /* set up an xfer and queue. Wait for completion */ 1463 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1464 ata_c->flags |= AT_POLL; 1465 if (ata_c->flags & AT_POLL) 1466 xfer->c_flags |= C_POLL; 1467 if (ata_c->flags & AT_WAIT) 1468 xfer->c_flags |= C_WAIT; 1469 xfer->c_drive = drvp->drive; 1470 xfer->c_databuf = ata_c->data; 1471 xfer->c_bcount = ata_c->bcount; 1472 xfer->ops = &wdc_cmd_xfer_ops; 1473 1474 ata_exec_xfer(chp, xfer); 1475 } 1476 1477 static int 1478 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1479 { 1480 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1481 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1482 int drive = xfer->c_drive; 1483 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1484 struct ata_command *ata_c = &xfer->c_ata_c; 1485 int tfd; 1486 1487 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1488 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1489 xfer->c_drive), DEBUG_FUNCS); 1490 1491 if (wdc->select) 1492 wdc->select(chp,drive); 1493 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1494 WDSD_IBM | (drive << 4)); 1495 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1496 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1497 case WDCWAIT_OK: 1498 break; 1499 case WDCWAIT_TOUT: 1500 ata_c->flags |= AT_TIMEOU; 1501 return ATASTART_ABORT; 1502 case WDCWAIT_THR: 1503 return ATASTART_TH; 1504 } 1505 if (ata_c->flags & AT_POLL) { 1506 /* polled command, disable interrupts */ 1507 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1508 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1509 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 1510 } 1511 if ((ata_c->flags & AT_LBA48) != 0) { 1512 wdccommandext(chp, drive, ata_c->r_command, 1513 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1514 ata_c->r_device & ~0x10); 1515 } else { 1516 wdccommand(chp, drive, ata_c->r_command, 1517 (ata_c->r_lba >> 8) & 0xffff, 1518 WDSD_IBM | (drive << 4) | 1519 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1520 ((ata_c->r_lba >> 24) & 0x0f), 1521 ata_c->r_lba & 0xff, 1522 ata_c->r_count & 0xff, 1523 ata_c->r_features & 0xff); 1524 } 1525 1526 if ((ata_c->flags & AT_POLL) == 0) { 1527 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1528 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1529 wdctimeout, chp); 1530 return ATASTART_STARTED; 1531 } 1532 1533 /* 1534 * Polled command. Wait for drive ready or drq. Done in intr(). 1535 * Wait for at last 400ns for status bit to be valid. 1536 */ 1537 delay(10); /* 400ns delay */ 1538 return ATASTART_POLL; 1539 } 1540 1541 static int 1542 __wdccommand_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1543 { 1544 __wdccommand_intr(chp, xfer, 0); 1545 return ATAPOLL_DONE; 1546 } 1547 1548 static int 1549 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1550 { 1551 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1552 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1553 struct ata_command *ata_c = &xfer->c_ata_c; 1554 int bcount = ata_c->bcount; 1555 char *data = ata_c->data; 1556 int wflags, tfd; 1557 int drive_flags; 1558 1559 if (ata_c->r_command == WDCC_IDENTIFY || 1560 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1561 /* 1562 * The IDENTIFY data has been designed as an array of 1563 * u_int16_t, so we can byteswap it on the fly. 1564 * Historically it's what we have always done so keeping it 1565 * here ensure binary backward compatibility. 1566 */ 1567 drive_flags = ATA_DRIVE_NOSTREAM | 1568 chp->ch_drive[xfer->c_drive].drive_flags; 1569 } else { 1570 /* 1571 * Other data structure are opaque and should be transferred 1572 * as is. 1573 */ 1574 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1575 } 1576 1577 #ifdef WDC_NO_IDS 1578 wflags = AT_POLL; 1579 #else 1580 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1581 /* both wait and poll, we can kpause here */ 1582 wflags = AT_WAIT | AT_POLL; 1583 } else { 1584 wflags = AT_POLL; 1585 } 1586 #endif 1587 1588 ata_channel_lock(chp); 1589 1590 again: 1591 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1592 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1593 xfer->c_drive), DEBUG_INTR); 1594 /* 1595 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1596 * Reselect again, it doesn't hurt for others commands, and the time 1597 * penalty for the extra register write is acceptable, 1598 * wdc_exec_command() isn't called often (mostly for autoconfig) 1599 */ 1600 if ((xfer->c_flags & C_ATAPI) != 0) { 1601 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1602 WDSD_IBM | (xfer->c_drive << 4)); 1603 } 1604 if ((ata_c->flags & AT_XFDONE) != 0) { 1605 /* 1606 * We have completed a data xfer. The drive should now be 1607 * in its initial state 1608 */ 1609 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1610 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1611 wflags, &tfd) == WDCWAIT_TOUT) { 1612 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1613 ata_channel_unlock(chp); 1614 return 0; /* IRQ was not for us */ 1615 } 1616 ata_c->flags |= AT_TIMEOU; 1617 } 1618 goto out; 1619 } 1620 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1621 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1622 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1623 ata_channel_unlock(chp); 1624 return 0; /* IRQ was not for us */ 1625 } 1626 ata_c->flags |= AT_TIMEOU; 1627 goto out; 1628 } 1629 if (wdc->irqack) 1630 wdc->irqack(chp); 1631 if (ata_c->flags & AT_READ) { 1632 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1633 ata_c->flags |= AT_TIMEOU; 1634 goto out; 1635 } 1636 wdc->datain_pio(chp, drive_flags, data, bcount); 1637 /* at this point the drive should be in its initial state */ 1638 ata_c->flags |= AT_XFDONE; 1639 /* 1640 * XXX checking the status register again here cause some 1641 * hardware to timeout. 1642 */ 1643 } else if (ata_c->flags & AT_WRITE) { 1644 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1645 ata_c->flags |= AT_TIMEOU; 1646 goto out; 1647 } 1648 wdc->dataout_pio(chp, drive_flags, data, bcount); 1649 ata_c->flags |= AT_XFDONE; 1650 if ((ata_c->flags & AT_POLL) == 0) { 1651 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1652 callout_reset(&chp->c_timo_callout, 1653 mstohz(ata_c->timeout), wdctimeout, chp); 1654 ata_channel_unlock(chp); 1655 return 1; 1656 } else { 1657 goto again; 1658 } 1659 } 1660 out: 1661 if (ATACH_ST(tfd) & WDCS_DWF) 1662 ata_c->flags |= AT_DF; 1663 if (ATACH_ST(tfd) & WDCS_ERR) { 1664 ata_c->flags |= AT_ERROR; 1665 ata_c->r_error = ATACH_ST(tfd); 1666 } 1667 1668 ata_channel_unlock(chp); 1669 1670 __wdccommand_done(chp, xfer); 1671 return 1; 1672 } 1673 1674 static void 1675 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1676 { 1677 struct atac_softc *atac = chp->ch_atac; 1678 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1679 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1680 struct ata_command *ata_c = &xfer->c_ata_c; 1681 bool start = true; 1682 1683 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1684 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1685 ata_c->flags), DEBUG_FUNCS); 1686 1687 if (ata_waitdrain_xfer_check(chp, xfer)) { 1688 start = false; 1689 goto out; 1690 } 1691 1692 if ((ata_c->flags & AT_READREG) != 0 && 1693 device_is_active(atac->atac_dev) && 1694 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1695 ata_c->r_status = bus_space_read_1(wdr->cmd_iot, 1696 wdr->cmd_iohs[wd_status], 0); 1697 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1698 wdr->cmd_iohs[wd_error], 0); 1699 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1700 wdr->cmd_iohs[wd_seccnt], 0); 1701 ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot, 1702 wdr->cmd_iohs[wd_sector], 0) << 0; 1703 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1704 wdr->cmd_iohs[wd_cyl_lo], 0) << 8; 1705 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1706 wdr->cmd_iohs[wd_cyl_hi], 0) << 16; 1707 ata_c->r_device = bus_space_read_1(wdr->cmd_iot, 1708 wdr->cmd_iohs[wd_sdh], 0); 1709 1710 if ((ata_c->flags & AT_LBA48) != 0) { 1711 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1712 if ((ata_c->flags & AT_POLL) != 0) 1713 bus_space_write_1(wdr->ctl_iot, 1714 wdr->ctl_ioh, wd_aux_ctlr, 1715 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1716 else 1717 bus_space_write_1(wdr->ctl_iot, 1718 wdr->ctl_ioh, wd_aux_ctlr, 1719 WDCTL_HOB|WDCTL_4BIT); 1720 } 1721 ata_c->r_count |= bus_space_read_1(wdr->cmd_iot, 1722 wdr->cmd_iohs[wd_seccnt], 0) << 8; 1723 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1724 wdr->cmd_iohs[wd_sector], 0) << 24; 1725 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1726 wdr->cmd_iohs[wd_cyl_lo], 0) << 32; 1727 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1728 wdr->cmd_iohs[wd_cyl_hi], 0) << 40; 1729 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1730 if ((ata_c->flags & AT_POLL) != 0) 1731 bus_space_write_1(wdr->ctl_iot, 1732 wdr->ctl_ioh, wd_aux_ctlr, 1733 WDCTL_4BIT|WDCTL_IDS); 1734 else 1735 bus_space_write_1(wdr->ctl_iot, 1736 wdr->ctl_ioh, wd_aux_ctlr, 1737 WDCTL_4BIT); 1738 } 1739 } else { 1740 ata_c->r_lba |= 1741 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1742 } 1743 ata_c->r_device &= 0xf0; 1744 } 1745 1746 __wdccommand_done_end(chp, xfer); 1747 1748 ata_deactivate_xfer(chp, xfer); 1749 1750 out: 1751 if (ata_c->flags & AT_POLL) { 1752 /* enable interrupts */ 1753 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1754 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1755 wd_aux_ctlr, WDCTL_4BIT); 1756 delay(10); /* some drives need a little delay here */ 1757 } 1758 1759 if (start) 1760 atastart(chp); 1761 } 1762 1763 static void 1764 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1765 { 1766 struct ata_command *ata_c = &xfer->c_ata_c; 1767 1768 ata_c->flags |= AT_DONE; 1769 } 1770 1771 static void 1772 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1773 int reason) 1774 { 1775 struct ata_command *ata_c = &xfer->c_ata_c; 1776 bool deactivate = true; 1777 1778 switch (reason) { 1779 case KILL_GONE_INACTIVE: 1780 deactivate = false; 1781 /* FALLTHROUGH */ 1782 case KILL_GONE: 1783 ata_c->flags |= AT_GONE; 1784 break; 1785 case KILL_RESET: 1786 ata_c->flags |= AT_RESET; 1787 break; 1788 default: 1789 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1790 reason); 1791 panic("__wdccommand_kill_xfer"); 1792 } 1793 1794 __wdccommand_done_end(chp, xfer); 1795 1796 if (deactivate) 1797 ata_deactivate_xfer(chp, xfer); 1798 } 1799 1800 /* 1801 * Send a command. The drive should be ready. 1802 * Assumes interrupts are blocked. 1803 */ 1804 void 1805 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1806 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1807 u_int8_t features) 1808 { 1809 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1810 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1811 1812 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1813 "sector=%d count=%d features=%d\n", 1814 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1815 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1816 1817 if (wdc->select) 1818 wdc->select(chp,drive); 1819 1820 /* Select drive, head, and addressing mode. */ 1821 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1822 WDSD_IBM | (drive << 4) | head); 1823 /* Load parameters into the wd_features register. */ 1824 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1825 features); 1826 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1827 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1828 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1829 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1830 0, cylin >> 8); 1831 1832 /* Send command. */ 1833 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1834 return; 1835 } 1836 1837 /* 1838 * Send a 48-bit addressing command. The drive should be ready. 1839 * Assumes interrupts are blocked. 1840 */ 1841 void 1842 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1843 u_int64_t blkno, u_int16_t count, u_int16_t features, u_int8_t device) 1844 { 1845 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1846 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1847 1848 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%02x " 1849 "blkno=0x%012"PRIx64" count=0x%04x features=0x%04x " 1850 "device=0x%02x\n", device_xname(chp->ch_atac->atac_dev), 1851 chp->ch_channel, drive, command, blkno, count, features, device), 1852 DEBUG_FUNCS); 1853 1854 KASSERT(drive < wdc->wdc_maxdrives); 1855 1856 if (wdc->select) 1857 wdc->select(chp,drive); 1858 1859 /* Select drive, head, and addressing mode. */ 1860 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1861 (drive << 4) | device); 1862 1863 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1864 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1865 0, features); 1866 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1867 0, count); 1868 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1869 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1870 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1871 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1872 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1873 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1874 } else { 1875 /* previous */ 1876 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1877 0, features >> 8); 1878 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1879 0, count >> 8); 1880 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1881 0, blkno >> 24); 1882 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1883 0, blkno >> 32); 1884 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1885 0, blkno >> 40); 1886 1887 /* current */ 1888 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1889 0, features); 1890 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1891 0, count); 1892 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1893 0, blkno); 1894 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1895 0, blkno >> 8); 1896 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1897 0, blkno >> 16); 1898 } 1899 1900 /* Send command. */ 1901 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1902 return; 1903 } 1904 1905 /* 1906 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1907 * tested by the caller. 1908 */ 1909 void 1910 wdccommandshort(struct ata_channel *chp, int drive, int command) 1911 { 1912 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1913 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1914 1915 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1916 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1917 command), DEBUG_FUNCS); 1918 1919 if (wdc->select) 1920 wdc->select(chp,drive); 1921 1922 /* Select drive. */ 1923 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1924 WDSD_IBM | (drive << 4)); 1925 1926 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1927 } 1928 1929 static void 1930 __wdcerror(struct ata_channel *chp, const char *msg) 1931 { 1932 struct atac_softc *atac = chp->ch_atac; 1933 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 1934 1935 if (xfer == NULL) 1936 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1937 chp->ch_channel, msg); 1938 else 1939 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1940 chp->ch_channel, xfer->c_drive, msg); 1941 } 1942 1943 /* 1944 * the bit bucket 1945 */ 1946 void 1947 wdcbit_bucket(struct ata_channel *chp, int size) 1948 { 1949 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1950 1951 for (; size >= 2; size -= 2) 1952 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1953 if (size) 1954 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1955 } 1956 1957 static void 1958 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1959 { 1960 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1961 1962 if ((chp->ch_atac->atac_cap & ATAC_CAP_DATA16) == 0) { 1963 /* 1964 * ATA_DRIVE_NOSTREAM is used for the IDENTIFY 1965 * command for ... reasons. Bad reasons, but 1966 * reasons nonetheless. So, emulate it as if 1967 * it were 16-bit PIO. 1968 */ 1969 if (flags & ATA_DRIVE_NOSTREAM) { 1970 uint8_t *cp = bf; 1971 for (size_t i = 0; i < len; i++) { 1972 cp[i ^ 1] = bus_space_read_1(wdr->cmd_iot, 1973 wdr->cmd_iohs[wd_data], 0); 1974 } 1975 return; 1976 } 1977 bus_space_read_multi_1(wdr->cmd_iot, 1978 wdr->cmd_iohs[wd_data], 0, bf, len); 1979 return; 1980 } 1981 1982 #ifndef __NO_STRICT_ALIGNMENT 1983 if ((uintptr_t)bf & 1) 1984 goto unaligned; 1985 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1986 goto unaligned; 1987 #endif 1988 1989 if (flags & ATA_DRIVE_NOSTREAM) { 1990 #if !defined(__BUS_SPACE_HAS_STREAM_METHODS) && _BYTE_ORDER == _BIG_ENDIAN 1991 /* 1992 * Because consumers of IDENTIFY are too lazy to byte-swap 1993 * their own payload, we have to do it ourselves here. 1994 * XXX THIS IS SO DUMB! FIX CONSUMERS OF IDENTIFY!!! 1995 * 1996 * Don't even try to deal with 32-bit PIO in this situation. 1997 */ 1998 KASSERT((flags & ATA_DRIVE_CAP32) == 0); 1999 uint16_t *p16 = bf; 2000 for (; len > 1; len -= 2) { 2001 *p16++ = 2002 bswap16(bus_space_read_2(wdr->cmd_iot, 2003 wdr->cmd_iohs[wd_data], 2004 0)); 2005 } 2006 bf = (void *)p16; 2007 #else 2008 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 2009 bus_space_read_multi_4(wdr->data32iot, 2010 wdr->data32ioh, 0, bf, len >> 2); 2011 bf = (char *)bf + (len & ~3); 2012 len &= 3; 2013 } 2014 if (len > 1) { 2015 bus_space_read_multi_2(wdr->cmd_iot, 2016 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2017 bf = (char *)bf + (len & ~1); 2018 len &= 1; 2019 } 2020 #endif 2021 } else { 2022 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 2023 bus_space_read_multi_stream_4(wdr->data32iot, 2024 wdr->data32ioh, 0, bf, len >> 2); 2025 bf = (char *)bf + (len & ~3); 2026 len &= 3; 2027 } 2028 if (len > 1) { 2029 bus_space_read_multi_stream_2(wdr->cmd_iot, 2030 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2031 bf = (char *)bf + (len & ~1); 2032 len &= 1; 2033 } 2034 } 2035 if (len) 2036 *((uint8_t *)bf) = bus_space_read_1(wdr->cmd_iot, 2037 wdr->cmd_iohs[wd_data], 0); 2038 return; 2039 2040 #ifndef __NO_STRICT_ALIGNMENT 2041 unaligned: 2042 if (flags & ATA_DRIVE_NOSTREAM) { 2043 #if !defined(__BUS_SPACE_HAS_STREAM_METHODS) && _BYTE_ORDER == _BIG_ENDIAN 2044 KASSERT((flags & ATA_DRIVE_CAP32) == 0); 2045 #else 2046 if (flags & ATA_DRIVE_CAP32) { 2047 while (len > 3) { 2048 uint32_t val; 2049 2050 val = bus_space_read_4(wdr->data32iot, 2051 wdr->data32ioh, 0); 2052 memcpy(bf, &val, 4); 2053 bf = (char *)bf + 4; 2054 len -= 4; 2055 } 2056 } 2057 #endif 2058 while (len > 1) { 2059 uint16_t val; 2060 2061 val = bus_space_read_2(wdr->cmd_iot, 2062 wdr->cmd_iohs[wd_data], 0); 2063 #if !defined(__BUS_SPACE_HAS_STREAM_METHODS) && _BYTE_ORDER == _BIG_ENDIAN 2064 val = bswap16(val); 2065 #endif 2066 memcpy(bf, &val, 2); 2067 bf = (char *)bf + 2; 2068 len -= 2; 2069 } 2070 } else { 2071 if (flags & ATA_DRIVE_CAP32) { 2072 while (len > 3) { 2073 uint32_t val; 2074 2075 val = bus_space_read_stream_4(wdr->data32iot, 2076 wdr->data32ioh, 0); 2077 memcpy(bf, &val, 4); 2078 bf = (char *)bf + 4; 2079 len -= 4; 2080 } 2081 } 2082 while (len > 1) { 2083 uint16_t val; 2084 2085 val = bus_space_read_stream_2(wdr->cmd_iot, 2086 wdr->cmd_iohs[wd_data], 0); 2087 memcpy(bf, &val, 2); 2088 bf = (char *)bf + 2; 2089 len -= 2; 2090 } 2091 } 2092 #endif 2093 } 2094 2095 static void 2096 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 2097 { 2098 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 2099 2100 #if !defined(__BUS_SPACE_HAS_STREAM_METHODS) && _BYTE_ORDER == _BIG_ENDIAN 2101 /* 2102 * This should absolutely never be necessary. If it is, we 2103 * have bigger problems. 2104 */ 2105 KASSERT((flags & ATA_DRIVE_NOSTREAM) == 0); 2106 #endif 2107 2108 if ((chp->ch_atac->atac_cap & ATAC_CAP_DATA16) == 0) { 2109 /* 2110 * ATA_DRIVE_NOSTREAM is not exactly expected for 2111 * PIO writes, but emulate it as if it were 2112 * 16-bit PIO. 2113 */ 2114 if (flags & ATA_DRIVE_NOSTREAM) { 2115 uint8_t *cp = bf; 2116 for (size_t i = 0; i < len; i++) { 2117 bus_space_write_1(wdr->cmd_iot, 2118 wdr->cmd_iohs[wd_data], 0, 2119 cp[i ^ 1]); 2120 } 2121 return; 2122 } 2123 bus_space_write_multi_1(wdr->cmd_iot, 2124 wdr->cmd_iohs[wd_data], 0, bf, len); 2125 return; 2126 } 2127 2128 #ifndef __NO_STRICT_ALIGNMENT 2129 if ((uintptr_t)bf & 1) 2130 goto unaligned; 2131 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 2132 goto unaligned; 2133 #endif 2134 2135 if (flags & ATA_DRIVE_NOSTREAM) { 2136 if (flags & ATA_DRIVE_CAP32) { 2137 bus_space_write_multi_4(wdr->data32iot, 2138 wdr->data32ioh, 0, bf, len >> 2); 2139 bf = (char *)bf + (len & ~3); 2140 len &= 3; 2141 } 2142 if (len) { 2143 bus_space_write_multi_2(wdr->cmd_iot, 2144 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2145 } 2146 } else { 2147 if (flags & ATA_DRIVE_CAP32) { 2148 bus_space_write_multi_stream_4(wdr->data32iot, 2149 wdr->data32ioh, 0, bf, len >> 2); 2150 bf = (char *)bf + (len & ~3); 2151 len &= 3; 2152 } 2153 if (len) { 2154 bus_space_write_multi_stream_2(wdr->cmd_iot, 2155 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2156 } 2157 } 2158 return; 2159 2160 #ifndef __NO_STRICT_ALIGNMENT 2161 unaligned: 2162 if (flags & ATA_DRIVE_NOSTREAM) { 2163 if (flags & ATA_DRIVE_CAP32) { 2164 while (len > 3) { 2165 uint32_t val; 2166 2167 memcpy(&val, bf, 4); 2168 bus_space_write_4(wdr->data32iot, 2169 wdr->data32ioh, 0, val); 2170 bf = (char *)bf + 4; 2171 len -= 4; 2172 } 2173 } 2174 while (len > 1) { 2175 uint16_t val; 2176 2177 memcpy(&val, bf, 2); 2178 bus_space_write_2(wdr->cmd_iot, 2179 wdr->cmd_iohs[wd_data], 0, val); 2180 bf = (char *)bf + 2; 2181 len -= 2; 2182 } 2183 } else { 2184 if (flags & ATA_DRIVE_CAP32) { 2185 while (len > 3) { 2186 uint32_t val; 2187 2188 memcpy(&val, bf, 4); 2189 bus_space_write_stream_4(wdr->data32iot, 2190 wdr->data32ioh, 0, val); 2191 bf = (char *)bf + 4; 2192 len -= 4; 2193 } 2194 } 2195 while (len > 1) { 2196 uint16_t val; 2197 2198 memcpy(&val, bf, 2); 2199 bus_space_write_stream_2(wdr->cmd_iot, 2200 wdr->cmd_iohs[wd_data], 0, val); 2201 bf = (char *)bf + 2; 2202 len -= 2; 2203 } 2204 } 2205 #endif 2206 } 2207
Indexes created Fri Aug 28 00:25:22 UTC 2026