| /src/external/bsd/openldap/dist/include/ |
| ldap_avl.h | 69 #define RH 1
71 #define avl_bf2str(bf) ((bf) == -1 ? "LH" : (bf) == 0 ? "EH" : (bf) == 1 ? "RH" : "(unknown)" )
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| /src/games/sail/ |
| pl_6.c | 65 repairs = &mf->RH;
|
| extern.h | 159 char RH; /* 224 */
|
| pl_7.c | 669 if (mf->RH)
670 wprintw(slot_w, "%dRH", mf->RH);
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 510 SDValue LL, LH, RL, RH, CL, CH;
513 GetSplitOp(N->getOperand(2), RL, RH);
543 Hi = DAG.getNode(N->getOpcode(), dl, LH.getValueType(), CH, LH, RH);
548 SDValue LL, LH, RL, RH;
551 GetSplitOp(N->getOperand(3), RL, RH);
556 N->getOperand(1), LH, RH, N->getOperand(4));
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| LegalizeIntegerTypes.cpp | 3284 SDValue LL, LH, RL, RH;
3286 GetExpandedInteger(N->getOperand(1), RL, RH);
3288 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
3297 SDValue LL, LH, RL, RH;
3299 GetExpandedInteger(N->getOperand(1), RL, RH);
3303 LL, LH, RL, RH))
3360 DAG.getNode(ISD::MUL, dl, NVT, RH, LL),
3450 SDValue LL, LH, RL, RH;
3452 GetExpandedInteger(RHS, RL, RH);
3458 LL, LH, RL, RH)) {
[all...] |
| TargetLowering.cpp | 6258 SDValue LH, SDValue RL, SDValue RH) const {
6277 // LL, LH, RL, and RH must be either all NULL or all set to a value.
6278 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
6279 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
6346 if (!LH.getNode() && !RH.getNode() &&
6351 RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift);
6352 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
6364 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
[all...] |
| LegalizeVectorTypes.cpp | 1890 SDValue LL, LH, RL, RH;
1899 GetSplitVector(N->getOperand(1), RL, RH);
1901 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1904 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonBitSimplify.cpp | 1709 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2);
1711 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, RH.Reg, RH.Sub, MRI);
1764 unsigned B, RegHalf &RH);
1805 // set the information about the found register in RH.
1807 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) {
1874 RH.Reg = Reg;
1875 RH.Sub = Sub;
1876 RH.Low = Low;
1878 if (!HBS::getFinalVRegClass(RH, MRI)
[all...] |
| HexagonConstPropagation.cpp | 1868 bool evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, const CellMap &Inputs,
2522 bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH,
2524 assert(Inputs.has(RL.Reg) && Inputs.has(RH.Reg));
2526 if (!getCell(RL, Inputs, LSL) || !getCell(RH, Inputs, LSH))
|
| /src/external/bsd/openldap/dist/libraries/libldap/ |
| tavl.c | 47 static const int avl_bfs[] = {LH, RH};
|
| avl.c | 60 static const int avl_bfs[] = {LH, RH};
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| /src/crypto/external/bsd/heimdal/dist/tests/kdc/ |
| check-kdc.in | 49 RH=TEST-HTTP.H5L.SE
186 ${RH} || exit 1
286 ${kadmin} add -p foo --use-defaults foo@${RH} || exit 1
383 ${kinit} --password-file=${objdir}/foopassword foo@${RH} || \
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 675 SDValue LH, RH;
678 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
684 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH);
686 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH);
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| LowerMatrixIntrinsics.cpp | 1058 Value *RH = Builder.CreateExtractElement(
1061 Value *Splat = Builder.CreateVectorSplat(BlockSize, RH, "splat");
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetLowering.h | 4327 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
4333 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
4342 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
4347 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
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| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 3524 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
3529 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
3534 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
3539 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
3545 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
|
