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    Searched refs:RING_MI_MODE (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_engine_cs.c 883 const i915_reg_t mode = RING_MI_MODE(base);
912 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1052 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
1305 ENGINE_READ(engine, RING_MI_MODE),
1306 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
intel_ring_submission.c 590 WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
617 RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING));
619 RING_MI_MODE(engine->mmio_base),
733 RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1810 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
intel_lrc.c 1186 pr_err("%s: context submitted with STOP_RING [%08x] in RING_MI_MODE\n",
3430 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
3444 if (ENGINE_READ_FW(engine, RING_MI_MODE) & STOP_RING) {
3445 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
selftest_lrc.c 3796 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)),
3798 "RING_MI_MODE"
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
mmio_context.c 75 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
127 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
handlers.c 1934 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_pmu.c 329 val = ENGINE_READ_FW(engine, RING_MI_MODE);
i915_gpu_error.c 1158 ee->mode = ENGINE_READ(engine, RING_MI_MODE);
i915_reg.h 2658 #define RING_MI_MODE(base) _MMIO((base) + 0x9c)

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