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    Searched refs:RISCVII (Results 1 - 12 of 12) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
RISCVBaseInfo.cpp 110 unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW,
125 RISCVII::VLMUL VLMUL = getVLMUL(VType);
131 case RISCVII::VLMUL::LMUL_RESERVED:
133 case RISCVII::VLMUL::LMUL_1:
134 case RISCVII::VLMUL::LMUL_2:
135 case RISCVII::VLMUL::LMUL_4:
136 case RISCVII::VLMUL::LMUL_8: {
141 case RISCVII::VLMUL::LMUL_F2:
142 case RISCVII::VLMUL::LMUL_F4:
143 case RISCVII::VLMUL::LMUL_F8:
    [all...]
RISCVMCCodeEmitter.cpp 273 unsigned MIFrm = RISCVII::getFormat(Desc.TSFlags);
301 if (MIFrm == RISCVII::InstFormatI)
303 else if (MIFrm == RISCVII::InstFormatS)
314 if (MIFrm == RISCVII::InstFormatI)
316 else if (MIFrm == RISCVII::InstFormatS)
331 if (MIFrm == RISCVII::InstFormatI)
333 else if (MIFrm == RISCVII::InstFormatS)
363 } else if (MIFrm == RISCVII::InstFormatB) {
365 } else if (MIFrm == RISCVII::InstFormatCJ) {
367 } else if (MIFrm == RISCVII::InstFormatCB)
    [all...]
RISCVBaseInfo.h 24 // RISCVII - This namespace holds all of the target specific flags that
26 namespace RISCVII {
156 } // namespace RISCVII
322 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
325 inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
327 return static_cast<RISCVII::VLMUL>(VLMUL);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVMCInstLower.cpp 37 case RISCVII::MO_None:
40 case RISCVII::MO_CALL:
43 case RISCVII::MO_PLT:
46 case RISCVII::MO_LO:
49 case RISCVII::MO_HI:
52 case RISCVII::MO_PCREL_LO:
55 case RISCVII::MO_PCREL_HI:
58 case RISCVII::MO_GOT_HI:
61 case RISCVII::MO_TPREL_LO:
64 case RISCVII::MO_TPREL_HI
    [all...]
RISCVISelDAGToDAG.cpp 111 unsigned NF, RISCVII::VLMUL LMUL) {
115 case RISCVII::VLMUL::LMUL_F8:
116 case RISCVII::VLMUL::LMUL_F4:
117 case RISCVII::VLMUL::LMUL_F2:
118 case RISCVII::VLMUL::LMUL_1:
120 case RISCVII::VLMUL::LMUL_2:
122 case RISCVII::VLMUL::LMUL_4:
169 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
210 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
254 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT)
    [all...]
RISCVMergeBaseOffset.cpp 83 HiLUI.getOperand(1).getTargetFlags() != RISCVII::MO_HI ||
91 LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO ||
151 if (AddiImmOp.getTargetFlags() != RISCVII::MO_None)
158 LuiImmOp.getTargetFlags() != RISCVII::MO_None ||
RISCVExpandPseudoInsts.cpp 180 .addMBB(NewMBB, RISCVII::MO_PCREL_LO);
201 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
215 FlagsHi = RISCVII::MO_GOT_HI;
218 FlagsHi = RISCVII::MO_PCREL_HI;
230 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
237 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
RISCVISelLowering.h 471 static RISCVII::VLMUL getLMUL(MVT VT);
472 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
RISCVISelLowering.cpp 1038 RISCVII::VLMUL RISCVTargetLowering::getLMUL(MVT VT) {
1048 return RISCVII::VLMUL::LMUL_F8;
1050 return RISCVII::VLMUL::LMUL_F4;
1052 return RISCVII::VLMUL::LMUL_F2;
1054 return RISCVII::VLMUL::LMUL_1;
1056 return RISCVII::VLMUL::LMUL_2;
1058 return RISCVII::VLMUL::LMUL_4;
1060 return RISCVII::VLMUL::LMUL_8;
1064 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVII::VLMUL LMul) {
1068 case RISCVII::VLMUL::LMUL_F8
    [all...]
RISCVInstrInfo.cpp 663 .addMBB(&DestBB, RISCVII::MO_CALL);
693 // RISCVII::FormMask, but this can't be used for Pseudo instructions like
954 const unsigned Mask = RISCVII::MO_DIRECT_FLAG_MASK;
960 using namespace RISCVII;
1130 RISCVII::MO_CALL));
RISCVFrameLowering.cpp 988 .addExternalSymbol(SpillLibCall, RISCVII::MO_CALL)
1035 .addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL)
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/
RISCVAsmParser.cpp 1596 RISCVII::VLMUL VLMUL =
1597 static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
2485 RISCVII::VConstraintType Constraints =
2486 RISCVII::getConstraint(MCID.TSFlags);
2487 if (Constraints == RISCVII::NoConstraint)
2493 if (Constraints & RISCVII::VS2Constraint) {
2499 if ((Constraints & RISCVII::VS1Constraint) && (Inst.getOperand(2).isReg())) {
2505 if ((Constraints & RISCVII::VMConstraint) && (DestReg == RISCV::V0)) {

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