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    Searched refs:RLWINM (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/sljit/dist/sljit_src/
sljitNativePPC_32.c 44 (RLWINM | S(src) | A(dst) | ((from) << 6) | (31 << 1))
208 return push_inst(compiler, RLWINM | RC(flags) | S(src1) | A(dst) | (compiler->imm << 11) | ((31 - compiler->imm) << 1));
216 return push_inst(compiler, RLWINM | RC(flags) | S(src1) | A(dst) | (((32 - compiler->imm) & 0x1f) << 11) | (compiler->imm << 6) | (31 << 1));
sljitNativePPC_64.c 337 return push_inst(compiler, RLWINM | RC(flags) | S(src1) | A(dst) | (compiler->imm << 11) | ((31 - compiler->imm) << 1));
349 return push_inst(compiler, RLWINM | RC(flags) | S(src1) | A(dst) | (((32 - compiler->imm) & 0x1f) << 11) | (compiler->imm << 6) | (31 << 1));
sljitNativePPC_common.c 204 #define RLWINM (HI(21))
994 FAIL_IF(push_inst(compiler, RLWINM | S(OFFS_REG(arg)) | A(tmp_r) | (argw << 11) | ((31 - argw) << 1)));
1774 FAIL_IF(push_inst(compiler, RLWINM | S(OFFS_REG(dst)) | A(TMP_REG1) | (dstw << 11) | ((31 - dstw) << 1)));
2226 FAIL_IF(push_inst(compiler, RLWINM | S(dst) | A(dst) | ((1 + (bit)) << 11) | (31 << 6) | (31 << 1)));
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/AsmParser/
PPCAsmParser.cpp 856 TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec);
870 TmpInst.setOpcode(Opcode == PPC::EXTRWI ? PPC::RLWINM : PPC::RLWINM_rec);
913 TmpInst.setOpcode(Opcode == PPC::ROTRWI ? PPC::RLWINM : PPC::RLWINM_rec);
926 TmpInst.setOpcode(Opcode == PPC::SLWI ? PPC::RLWINM : PPC::RLWINM_rec);
939 TmpInst.setOpcode(Opcode == PPC::SRWI ? PPC::RLWINM : PPC::RLWINM_rec);
952 TmpInst.setOpcode(Opcode == PPC::CLRRWI ? PPC::RLWINM : PPC::RLWINM_rec);
966 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI ? PPC::RLWINM : PPC::RLWINM_rec);
1093 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINM_rec);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp 1389 // by rlwinm and friends in 64-bit mode).
1790 // In 64-bit mode, rlwinm and friends have a rotation operator that
2045 VRot = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2105 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
2126 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
2203 // done by rlwinm and friends).
2267 // done by rlwinm and friends).
3124 return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
3166 return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
3179 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0)
    [all...]
PPCInstrInfo.cpp 1716 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
1727 unsigned ShCode = Is64Bit ? PPC::RLWINM8 : PPC::RLWINM;
2660 if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
2675 NewOpC = MIOpC == PPC::RLWINM
2685 NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDIS_rec : PPC::ANDIS8_rec;
3254 Opc == PPC::RLWINM || Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8 ||
3697 if (SrcMI->getOpcode() != PPC::RLWINM &&
3705 "Invalid PPC::RLWINM Instruction!");
3714 "Invalid PPC::RLWINM Instruction!");
3762 if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8)
    [all...]
PPCRegisterInfo.cpp 772 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
804 // rlwinm rA, rA, ShiftBits, 0, 31.
805 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
850 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
851 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
963 // rlwinm rA, rA, ShiftBits, 0, 0.
964 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
PPCMIPeephole.cpp 180 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
990 case PPC::RLWINM:
PPCFastISel.cpp 1827 // Unsigned 32-bit extensions use RLWINM.
1836 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM),
2326 case PPC::RLWINM:
PPCFrameLowering.cpp 926 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
1451 BuildMI(*CurrentMBB, {MI}, DL, TII.get(PPC::RLWINM), ScratchReg)
PPCISelLowering.cpp 11241 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
11243 // rlwinm ptr, ptr1, 0, 0, 29
11257 // rlwinm SrwDest, SrwDest, 0, 24 [16], 31
11268 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg)
11283 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
11360 // the upper bits with a separate RLWINM.
11361 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::RLWINM), dest)
12247 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
12249 // rlwinm ptr, ptr1, 0, 0, 29
12282 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/
PPCInstPrinter.cpp 114 if (MI->getOpcode() == PPC::RLWINM) {

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