HomeSort by: relevance | last modified time | path
    Searched refs:RREG32_NO_KIQ (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_mxgpu_ai.c 61 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
71 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
143 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
185 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
232 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
285 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
amdgpu_mxgpu_nv.c 61 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
71 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
145 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
187 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
234 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_INT_CNTL));
290 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_INT_CNTL));
amdgpu_mxgpu_vi.c 328 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
333 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
342 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
350 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
361 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0);
377 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
382 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);
398 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
408 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
507 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL)
    [all...]
amdgpu_vega10_ih.c 401 wptr = RREG32_NO_KIQ(reg);
426 tmp = RREG32_NO_KIQ(reg);
501 v = RREG32_NO_KIQ(reg_rptr);
amdgpu_navi10_ih.c 225 wptr = RREG32_NO_KIQ(reg);
241 tmp = RREG32_NO_KIQ(reg);
amdgpu_virt.c 40 return RREG32_NO_KIQ(0xc040) == 0xffffffff;
amdgpu_vi.c 99 (void)RREG32_NO_KIQ(mmPCIE_INDEX);
100 r = RREG32_NO_KIQ(mmPCIE_DATA);
111 (void)RREG32_NO_KIQ(mmPCIE_INDEX);
113 (void)RREG32_NO_KIQ(mmPCIE_DATA);
124 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);
amdgpu_gmc_v10_0.c 288 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
305 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
309 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
amdgpu_gmc_v9_0.c 519 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
536 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
539 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
amdgpu.h 1046 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
amdgpu_ttm.c 1712 value = RREG32_NO_KIQ(mmMM_DATA);
2459 value = RREG32_NO_KIQ(mmMM_DATA);
amdgpu_device.c 208 *buf++ = RREG32_NO_KIQ(mmMM_DATA);

Completed in 23 milliseconds