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    Searched refs:RREG32_PCIE (Results 1 - 25 of 27) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_nbio_v6_1.c 155 def = data = RREG32_PCIE(smnCPM_CONTROL);
183 def = data = RREG32_PCIE(smnPCIE_CNTL2);
204 data = RREG32_PCIE(smnCPM_CONTROL);
209 data = RREG32_PCIE(smnPCIE_CNTL2);
270 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
277 def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
amdgpu_nbio_v2_3.c 206 def = data = RREG32_PCIE(smnCPM_CONTROL);
232 def = data = RREG32_PCIE(smnPCIE_CNTL2);
253 data = RREG32_PCIE(smnCPM_CONTROL);
258 data = RREG32_PCIE(smnPCIE_CNTL2);
319 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
amdgpu_nbio_v7_0.c 168 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
206 def = data = RREG32_PCIE(smnPCIE_CNTL2);
227 data = RREG32_PCIE(smnCPM_CONTROL);
232 data = RREG32_PCIE(smnPCIE_CNTL2);
amdgpu_nbio_v7_4.c 212 def = data = RREG32_PCIE(smnPCIE_CNTL2);
233 data = RREG32_PCIE(smnCPM_CONTROL);
238 data = RREG32_PCIE(smnPCIE_CNTL2);
495 global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO);
500 parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2);
508 central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS);
521 int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI);
amdgpu_umc_v6_1.c 121 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
125 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
136 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
333 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
amdgpu_cik.c 1482 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
1521 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
1528 tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
1561 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
1565 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
1612 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
1636 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
1641 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
1664 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1671 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3)
    [all...]
amdgpu_soc15.c 879 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
884 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
885 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
928 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
933 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
934 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
965 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
966 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
amdgpu_vi.c 1053 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
1058 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1059 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1067 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
1068 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
1428 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1691 data = RREG32_PCIE(ixPCIE_CNTL2);
amdgpu_si.c 1399 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
1404 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1405 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1413 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
1414 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
1715 tmp = RREG32_PCIE(PCIE_LC_STATUS1);
1896 orig = data = RREG32_PCIE(PCIE_P_CNTL);
2059 orig = data = RREG32_PCIE(PCIE_CNTL2);
2067 data = RREG32_PCIE(PCIE_LC_STATUS1);
amdgpu_df_v3_6.c 714 base_addr_reg_val = RREG32_PCIE(smnDF_CS_UMC_AON0_DramBaseAddress0 +
739 xgmi_node_id = RREG32_PCIE(smnDF_CS_UMC_AON0_DramLimitAddress0 +
amdgpu_cgs.c 73 return RREG32_PCIE(index);
amdgpu_psp_v3_1.c 545 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000);
amdgpu_debugfs.c 263 value = RREG32_PCIE(*pos >> 2);
amdgpu.h 1062 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
amdgpu_gmc_v7_0.c 878 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_r300.c 100 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
102 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
210 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
230 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
568 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
584 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
586 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
602 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
629 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
631 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE)
    [all...]
radeon_si.c 5579 orig = data = RREG32_PCIE(PCIE_CNTL2);
7167 tmp = RREG32_PCIE(PCIE_LC_STATUS1);
7310 orig = data = RREG32_PCIE(PCIE_P_CNTL);
7473 orig = data = RREG32_PCIE(PCIE_CNTL2);
7481 data = RREG32_PCIE(PCIE_LC_STATUS1);
radeon_rv6xx_dpm.c 135 tmp = RREG32_PCIE(PCIE_P_CNTL);
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_smu9_smumgr.c 48 mp1_fw_flags = RREG32_PCIE(MP1_Public |
amdgpu_vega20_smumgr.c 57 mp1_fw_flags = RREG32_PCIE(MP1_Public |
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_smu_v12_0.c 121 mp1_fw_flags = RREG32_PCIE(MP1_Public |
amdgpu_navi10_ppt.c 325 mp0_fw_intf = RREG32_PCIE(MP0_Public |
832 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
835 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
amdgpu_smu_v11_0.c 218 mp1_fw_flags = RREG32_PCIE(MP1_Public |
237 mp1_fw_flags = RREG32_PCIE(MP1_Public |
amdgpu_vega20_ppt.c 1070 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1073 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_vega20_hwmgr.c 3365 current_gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
3368 current_lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &

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