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    Searched refs:RREG32_PLL (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_clocks.c 50 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
56 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
63 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
80 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
86 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
93 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
127 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
157 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
205 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
221 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV)
    [all...]
radeon_legacy_crtc.c 229 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
237 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
256 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
264 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
870 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
919 RREG32_PLL(RADEON_P2PLL_CNTL));
938 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
950 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
951 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
1025 RREG32_PLL(RADEON_PPLL_CNTL))
    [all...]
radeon_rs600.c 258 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
275 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
287 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
295 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
302 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
radeon_combios.c 1156 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1161 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
2996 val = RREG32_PLL(reg);
3075 (RREG32_PLL
3125 tmp = RREG32_PLL(addr);
3143 (RREG32_PLL
3151 if (RREG32_PLL
3159 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3163 RREG32_PLL
radeon_r420.c 209 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
radeon_legacy_encoders.c 122 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
665 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
1588 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
radeon_rv515.c 515 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
517 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
519 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
radeon_r100.c 385 sclk_cntl = RREG32_PLL(SCLK_CNTL);
386 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
388 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
2709 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
3905 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
radeon_legacy_tv.c 291 save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL);
radeon_r300.c 1400 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
radeon.h 2599 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2632 uint32_t tmp_ = RREG32_PLL(reg); \
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu.h 1091 uint32_t tmp_ = RREG32_PLL(reg); \

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