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    Searched refs:RSrc (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/ExecutionEngine/Orc/
OrcRemoteTargetServer.h 367 Expected<std::vector<uint8_t>> handleReadMem(JITTargetAddress RSrc,
369 uint8_t *Src = reinterpret_cast<uint8_t *>(static_cast<uintptr_t>(RSrc));
372 << format("0x%016x", RSrc) << "\n");
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 3670 Register RSrc = MI.getOperand(2).getReg();
3731 .addUse(RSrc) // rsrc
3759 Register RSrc = MI.getOperand(2).getReg();
3834 .addUse(RSrc) // rsrc
3963 Register RSrc = MI.getOperand(3 + OpOffset).getReg();
3999 MIB.addUse(RSrc) // rsrc
AMDGPURegisterBankInfo.cpp 365 // rsrc, voffset, offset
394 // rsrc, offset
1309 // If this intrinsic has a sampler, it immediately follows rsrc.
1471 Register RSrc = MI.getOperand(1).getReg();
1494 .addUse(RSrc) // rsrc
1515 OpsToWaterfall.insert(RSrc);
1763 Register RSrc = MI.getOperand(2).getReg();
1802 MIB.addUse(RSrc)
3185 // If this has a sampler, it immediately follows rsrc
    [all...]
AMDGPUInstructionSelector.cpp 2994 I.add(MI.getOperand(2)); // rsrc
3718 return {{[=](MachineInstrBuilder &MIB) { // rsrc
3760 return {{[=](MachineInstrBuilder &MIB) { // rsrc
3825 [=](MachineInstrBuilder &MIB) { // rsrc
3965 Register RSrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);
3993 .addDef(RSrc)
3999 return RSrc;
4167 [=](MachineInstrBuilder &MIB) { // rsrc
4198 [=](MachineInstrBuilder &MIB) { // rsrc
4227 [=](MachineInstrBuilder &MIB) { // rsrc
    [all...]
SIInstrInfo.cpp 319 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
320 if (!RSrc) // e.g. BUFFER_WBINVL1_VOL
322 BaseOps.push_back(RSrc);
5126 // unique value of \p Rsrc across all lanes. In the best case we execute 1
5131 const DebugLoc &DL, MachineOperand &Rsrc) {
5149 Register VRsrc = Rsrc.getReg();
5150 unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef());
5152 unsigned RegSize = TRI->getRegSizeInBits(Rsrc.getReg(), MRI);
5204 // Build scalar Rsrc.
5212 // Update Rsrc operand to use the SGPR Rsrc
    [all...]
AMDGPUISelDAGToDAG.cpp 195 SDValue Addr, SDValue &RSrc, SDValue &VAddr,
1520 SDValue Addr, SDValue &Rsrc,
1528 Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
1630 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
1637 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);

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