| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 36 const SmallVectorImpl<CCValAssign> &RVLocs,
243 SmallVector<CCValAssign, 16> RVLocs;
245 CCState RetCCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
364 return lowerCallResult(Chain, Glue, RVLocs, dl, DAG, InVals);
370 const SmallVectorImpl<CCValAssign> &RVLocs,
375 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
376 const CCValAssign &VA = RVLocs[i];
596 SmallVector<CCValAssign, 16> RVLocs;
597 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
616 SmallVector<CCValAssign, 16> RVLocs;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 508 SmallVector<CCValAssign, 16> RVLocs;
512 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
526 for (unsigned i = 0; i != RVLocs.size(); ++i) {
527 CCValAssign &VA = RVLocs[i];
554 SmallVector<CCValAssign, 16> RVLocs;
555 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
567 for (auto &Val : RVLocs) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 561 SmallVectorImpl<CCValAssign> &RVLocs,
728 SmallVector<CCValAssign, 16> RVLocs;
729 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
743 SmallVector<CCValAssign, 16> RVLocs;
750 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
754 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
760 for (unsigned i = 0; i != RVLocs.size(); ++i) {
761 CCValAssign &VA = RVLocs[i];
939 SmallVector<CCValAssign, 16> RVLocs;
940 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 1061 const SmallVectorImpl<CCValAssign> &RVLocs,
1066 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1067 const CCValAssign &VA = RVLocs[i];
1124 SmallVector<CCValAssign, 16> RVLocs;
1126 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1228 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals);
1426 SmallVector<CCValAssign, 16> RVLocs;
1427 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1448 SmallVector<CCValAssign, 16> RVLocs;
1451 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 540 SmallVector<CCValAssign, 16> RVLocs;
543 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
553 for (unsigned i = 0; i != RVLocs.size(); ++i) {
554 CCValAssign &VA = RVLocs[i];
779 SmallVector<CCValAssign, 16> RVLocs;
780 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
786 for (unsigned I = 0; I != RVLocs.size(); ++I) {
787 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
788 RVLocs[I].getValVT(), InFlag)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 214 SmallVector<CCValAssign, 16> RVLocs;
217 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
230 i != RVLocs.size();
232 CCValAssign &VA = RVLocs[i];
252 VA = RVLocs[++i]; // skip ahead to next loc
297 SmallVector<CCValAssign, 16> RVLocs;
300 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
314 for (unsigned i = 0; i != RVLocs.size(); ++i) {
315 CCValAssign &VA = RVLocs[i];
343 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 2028 SmallVector<CCValAssign, 16> RVLocs;
2029 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2033 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2036 MVT DestVT = RVLocs[0].getValVT();
2041 .addReg(RVLocs[0].getLocReg())
2042 .addReg(RVLocs[1].getLocReg()));
2044 UsedRegs.push_back(RVLocs[0].getLocReg());
2045 UsedRegs.push_back(RVLocs[1].getLocReg());
2050 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2051 MVT CopyVT = RVLocs[0].getValVT()
[all...] |
| ARMISelLowering.cpp | 2099 SmallVector<CCValAssign, 16> RVLocs;
2100 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2105 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2106 CCValAssign VA = RVLocs[i];
2125 VA = RVLocs[++i]; // skip ahead to next loc
2139 VA = RVLocs[++i]; // skip ahead to next loc
2143 VA = RVLocs[++i]; // skip ahead to next loc
2912 SmallVector<CCValAssign, 16> RVLocs;
2913 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2957 SmallVector<CCValAssign, 16> RVLocs;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 1398 SmallVector<CCValAssign, 16> RVLocs;
1399 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1410 for (CCValAssign const &RVLoc : RVLocs) {
1429 SmallVector<CCValAssign, 16> RVLocs;
1430 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1445 SmallVector<CCValAssign, 16> RVLocs;
1448 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1463 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1464 CCValAssign &VA = RVLocs[i];
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 69 SmallVector<CCValAssign, 16> RVLocs;
70 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
324 SmallVector<CCValAssign, 16> RVLocs;
327 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
337 for (unsigned i = 0; i != RVLocs.size(); ++i) {
338 CCValAssign &VA = RVLocs[i];
741 SmallVector<CCValAssign, 16> RVLocs;
742 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
753 for (unsigned i = 0; i != RVLocs.size(); ++i) {
754 CCValAssign &VA = RVLocs[i]
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 1500 SmallVector<CCValAssign, 16> RVLocs;
1501 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1503 CCValAssign &VA = RVLocs[0];
1504 assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1586 SmallVector<CCValAssign, 16> RVLocs;
1587 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1589 if (RVLocs.size() > 1)
|
| PPCISelLowering.cpp | 5080 SmallVector<CCValAssign, 16> RVLocs;
5081 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5090 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
5091 CCValAssign &VA = RVLocs[i];
5101 VA = RVLocs[++i]; // skip ahead to next loc
7438 SmallVector<CCValAssign, 16> RVLocs;
7439 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
7452 SmallVector<CCValAssign, 16> RVLocs;
7453 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
7464 for (unsigned i = 0, RealResIdx = 0; i != RVLocs.size(); ++i, ++RealResIdx)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 186 SmallVector<CCValAssign, 16> RVLocs;
187 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
204 SmallVector<CCValAssign, 16> RVLocs;
207 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
220 for (unsigned i = 0; i != RVLocs.size(); ++i) {
221 CCValAssign &VA = RVLocs[i];
352 SmallVector<CCValAssign, 16> RVLocs;
354 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
363 for (unsigned i = 0; i != RVLocs.size(); ++i) {
365 if (RVLocs[i].getValVT() == MVT::i1)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 1281 SmallVector<CCValAssign, 16> RVLocs;
1282 MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1289 if (RVLocs.size() != 1)
1292 MVT CopyVT = RVLocs[0].getValVT();
1302 ResultReg).addReg(RVLocs[0].getLocReg());
1303 CLI.InRegs.push_back(RVLocs[0].getLocReg());
|
| MipsISelLowering.cpp | 3484 SmallVector<CCValAssign, 16> RVLocs;
3485 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3494 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3495 CCValAssign &VA = RVLocs[i];
3498 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3499 RVLocs[i].getLocVT(), InFlag);
3764 SmallVector<CCValAssign, 16> RVLocs;
3765 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3797 SmallVector<CCValAssign, 16> RVLocs;
3801 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 838 SmallVector<CCValAssign, 16> RVLocs;
839 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
844 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
845 CCValAssign &VA = RVLocs[i];
1017 SmallVector<CCValAssign, 16> RVLocs;
1018 CCState CCInfo(CCID, IsVarArg, MF, RVLocs, *DAG.getContext());
1030 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1031 CCValAssign &VA = RVLocs[i];
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 3528 SmallVector<CCValAssign, 16> RVLocs;
3529 CCState CCRetInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs,
3535 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3536 CCValAssign &VA = RVLocs[i];
3578 CLI.NumResultRegs = RVLocs.size();
|
| X86ISelLowering.cpp | 2609 SmallVector<CCValAssign, 16> RVLocs;
2610 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2695 SmallVector<CCValAssign, 16> RVLocs;
2696 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2700 for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2702 CCValAssign &VA = RVLocs[I];
2776 Passv64i1ArgInRegs(dl, DAG, ValToCopy, RetVals, VA, RVLocs[++I],
2781 MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());
3040 SmallVector<CCValAssign, 16> RVLocs;
3041 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 3092 SmallVector<CCValAssign, 16> RVLocs;
3093 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
3097 if (RVLocs.size() != 1)
3101 MVT CopyVT = RVLocs[0].getValVT();
3110 .addReg(RVLocs[0].getLocReg());
3111 CLI.InRegs.push_back(RVLocs[0].getLocReg());
|
| AArch64ISelLowering.cpp | 5204 SmallVector<CCValAssign, 16> RVLocs;
5206 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5211 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5212 CCValAssign VA = RVLocs[i];
5973 SmallVector<CCValAssign, 16> RVLocs;
5974 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5988 SmallVector<CCValAssign, 16> RVLocs;
5989 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5997 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
5999 CCValAssign &VA = RVLocs[i]
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 2508 SmallVector<CCValAssign, 16> RVLocs;
2509 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2533 SmallVector<CCValAssign, 48> RVLocs;
2537 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2563 for (unsigned I = 0, RealRVLocIdx = 0, E = RVLocs.size(); I != E;
2565 CCValAssign &VA = RVLocs[I];
2631 SmallVector<CCValAssign, 16> RVLocs;
2632 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2637 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2638 CCValAssign VA = RVLocs[i]
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 7706 SmallVector<CCValAssign, 16> RVLocs;
7707 CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
7711 for (auto &VA : RVLocs) {
7740 SmallVector<CCValAssign, 16> RVLocs;
7741 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
7769 SmallVector<CCValAssign, 16> RVLocs;
7772 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
7778 if (CallConv == CallingConv::GHC && !RVLocs.empty())
7785 for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) {
7787 CCValAssign &VA = RVLocs[i]
[all...] |
