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    Searched refs:Reads (Results 1 - 22 of 22) sorted by relevancy

  /src/external/mpl/dhcp/dist/contrib/
3.0b1-lease-convert 78 Reads from the lease file listed on the command line (or stdin if not filename
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenSchedule.cpp 567 // Reads don't currently have sequence records, but it can be added later.
588 // Reserve idx=0 for invalid writes/reads.
658 // itinerary resources. Index reads and writes in separate domains.
687 dbgs() << "\n+++ SCHED READS and WRITES (collectSchedRW) +++\n";
756 IdxVec &Writes, IdxVec &Reads) const {
761 findRWs(ReadDefs, Reads, true);
874 IdxVec Writes, Reads;
876 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
879 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/{0});
926 for (unsigned int Read : SC.Reads)
    [all...]
CodeGenSchedule.h 70 // added. Note that implicit Reads (from ReadVariant) may have a Sequence
118 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
126 /// that mapped the itinerary class to the variant Writes or Reads.
133 IdxVec Reads;
153 makeArrayRef(Reads) == R;
562 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
638 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
SubtargetEmitter.cpp 1024 IdxVec Reads = SC.Reads;
1038 Reads.clear();
1040 Writes, Reads);
1049 Writes, Reads);
1149 for (unsigned UseIdx = 0, EndIdx = Reads.size();
1152 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
  /src/external/apache2/llvm/dist/llvm/lib/MCA/
InstrBuilder.cpp 297 // According to assumption 2. register reads start at #(NumExplicitDefs-1).
437 ID.Reads.resize(TotalUses);
445 ReadDescriptor &Read = ID.Reads[CurrentUse];
457 ReadDescriptor &Read = ID.Reads[CurrentUse + I];
481 ReadDescriptor &Read = ID.Reads[CurrentUse];
490 ID.Reads.resize(CurrentUse);
635 // Initialize Reads first.
637 for (const ReadDescriptor &RD : D.Reads) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CalcSpillWeights.cpp 253 bool Reads, Writes;
254 std::tie(Reads, Writes) = MI->readsWritesVirtualRegister(LI.reg());
255 Weight = LiveIntervals::getSpillWeight(Writes, Reads, &MBFI, *MI);
EarlyIfConversion.cpp 368 SmallVector<MCRegister, 8> Reads;
393 // Unless I reads Reg.
395 Reads.push_back(Reg.asMCReg());
398 while (!Reads.empty())
399 for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
MachineInstrBundle.cpp 293 RI.Reads = true;
RegisterCoalescer.cpp 302 /// If the given machine operand reads only undefined lanes add an undef
1751 bool Reads, Writes;
1752 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
1756 if (DstInt && !Reads && SubIdx && !UseMI->isDebugValue())
1757 Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI));
1767 MO.setIsUndef(!Reads);
3012 // No need to check the instruction defining VNI for reads.
InlineSpiller.cpp 581 if (!RI.Reads)
911 // Skip non-Defs, including undef uses and internal reads.
1071 // Find the slot index where this instruction reads and writes OldLI.
1110 if (RI.Reads)
MachinePipeliner.cpp 2561 bool Reads, Writes;
2562 std::tie(Reads, Writes) =
2564 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) {
2568 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) {
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
RegisterFile.h 268 MutableArrayRef<ReadState> Reads);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineInstrBundle.h 219 /// Reads - One of the operands read the virtual register. This does not
221 bool Reads;
  /src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
RegisterFile.cpp 399 MutableArrayRef<ReadState> Reads) {
400 if (Writes.size() != Reads.size())
403 // This logic assumes that writes and reads are contributed by a register move
422 const ReadState &RS = Reads[I];
429 ReadState &RS = Reads[I];
  /src/external/apache2/llvm/dist/clang/tools/scan-build-py/libscanbuild/
report.py 287 """ Reads and merges all .sarif files in the given output directory.
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
Instruction.h 10 /// This file defines abstractions used by the Pipeline to model register reads,
67 // reads. Implicit reads have negative indices. The actual operand index of an
141 // A list of dependent reads. Users is a set of dependent
142 // reads. A dependent read is added to the set only if CyclesLeft
171 // This method adds Use to the set of data dependent reads. IID is the
350 SmallVector<ReadDescriptor, 4> Reads; // Implicit reads are at the end.
  /src/external/gpl3/gcc.old/dist/libphobos/libdruntime/core/sys/windows/
winioctl.d 487 DWORD Reads;
  /src/external/gpl3/gcc.old/dist/libphobos/src/std/datetime/
timezone.d 198 // it reads a time zone file.
1868 use `PosixTimeZone` (which reads its information from the TZ Database
2642 Reads an int from a TZ file.
2657 Reads an array of values from a TZ file.
2672 Reads a `TempTTInfo` from a TZ file.
2837 $(LREF PosixTimeZone) (which reads its information from the TZ Database
3345 parseTZConversions reads in those conversions from windowsZones.xml so that
  /src/sys/arch/m68k/060sp/dist/
os.s 113 # Reads from data/instruction memory while in supervisor mode.
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 3329 bool Reads, Writes;
3330 std::tie(Reads, Writes) = StartMI->readsWritesVirtualRegister(RegNo);
3331 if (!Reads && !Writes) {
  /src/external/gpl3/gcc.old/dist/libphobos/src/std/
file.d 486 Reads and validates (using $(REF validate, std, utf)) a text file. S can be
1193 // Reads a time field from a stat_t with full precision.
5157 * Reads a file line by line and parses the line into a single value or a
  /src/external/gpl3/gcc.old/dist/libphobos/src/std/uni/
package.d 468 a handful of simple instructions and 2 array reads. Subsequent levels
734 // TODO: update to reflect all major CPUs supporting unaligned reads
1204 && hasUnalignedReads)) // this needs unaligned reads
1999 The name comes from the way the representation reads left to right.
7138 Reads one full grapheme cluster from an

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