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    Searched refs:Reg0 (Results 1 - 21 of 21) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsTargetStreamer.h 122 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
126 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
128 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
130 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
132 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
134 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
136 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
138 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
140 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
MipsSEFrameLowering.cpp 463 unsigned Reg0 =
469 std::swap(Reg0, Reg1);
472 MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
481 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true);
485 std::swap(Reg0, Reg1);
488 MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonPeephole.cpp 237 Register Reg0 = Op0.getReg();
238 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
242 if (Reg0.isVirtual()) {
244 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
HexagonBitTracker.cpp 314 unsigned Reg0 = Reg[0].Reg;
840 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs);
842 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs);
844 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs);
846 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
MipsTargetStreamer.cpp 169 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
173 TmpInst.addOperand(MCOperand::createReg(Reg0));
178 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
182 TmpInst.addOperand(MCOperand::createReg(Reg0));
188 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
190 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
193 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
195 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
208 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
213 TmpInst.addOperand(MCOperand::createReg(Reg0));
    [all...]
MipsMCCodeEmitter.cpp 98 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
103 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!");
104 if (Reg0 < Reg1)
107 if (Reg0 >= Reg1)
111 if (Reg1 >= Reg0)
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCRegisterInfo.h 747 uint16_t Reg0 = 0;
755 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
761 return Reg0;
766 return Reg0;
772 Reg0 = Reg1;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 2131 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2150 // VLD1/VLD2 fixed increment does not need Reg0 so only include it in
2153 Ops.push_back(Reg0);
2156 Ops.push_back(Reg0);
2169 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
2182 Ops.push_back(Reg0);
2186 Ops.push_back(Reg0);
2266 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2310 // VST1/VST2 fixed increment does not need Reg0 so only include it i
    [all...]
Thumb2SizeReduction.cpp 756 Register Reg0 = MI->getOperand(0).getReg();
762 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
765 if (Reg0 != Reg2) {
768 if (Reg1 != Reg0)
775 } else if (Reg0 != Reg1) {
780 MI->getOperand(CommOpIdx2).getReg() != Reg0)
787 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
ARMAsmPrinter.cpp 322 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
323 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
1362 // Add 's' bit operand (always reg0 for this)
1408 // Add 's' bit operand (always reg0 for this)
1417 // Add 's' bit operand (always reg0 for this)
1428 // Add 's' bit operand (always reg0 for this)
1469 // Add 's' bit operand (always reg0 for this)
1501 // Add 's' bit operand (always reg0 for this)
1606 // Add 's' bit operand (always reg0 for this)
1810 // Add 's' bit operand (always reg0 for this
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelDAGToDAG.cpp 224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
247 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
262 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetInstrInfo.cpp 184 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
206 if (HasDef && Reg0 == Reg1 &&
209 Reg0 = Reg2;
211 } else if (HasDef && Reg0 == Reg2 &&
214 Reg0 = Reg1;
228 CommutedMI->getOperand(0).setReg(Reg0);
RegAllocFast.cpp 1188 Register Reg0 = MO0.getReg();
1190 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0);
RegisterCoalescer.cpp 2606 Register Reg0;
2607 std::tie(Orig0, Reg0) = followCopyChain(Value0);
2608 if (Orig0 == Value1 && Reg0 == Other.Reg)
2618 return Orig0 == Orig1 && Reg0 == Reg1;
2624 return Orig0->def == Orig1->def && Reg0 == Reg1;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMInstPrinter.cpp 1437 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1440 printRegName(O, Reg0);
1450 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1453 printRegName(O, Reg0);
1505 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1508 printRegName(O, Reg0);
1552 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1555 printRegName(O, Reg0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ExpandPseudo.cpp 467 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0);
471 .addReg(Reg0, RegState::Define | getDeadRegState(DstIsDead));
501 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0);
514 MIBLo.addReg(Reg0, getKillRegState(SrcIsKill));
X86InstrInfo.cpp 5632 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
5642 if ((HasDef && Reg0 == Reg1 && Tied1) ||
5643 (HasDef && Reg0 == Reg2 && Tied2))
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FrameLowering.cpp 759 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
762 .addImm(Reg0)
772 Register Reg0 = MBBI->getOperand(1).getReg();
774 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR)
780 .addImm(RegInfo->getSEHRegNum(Reg0))
810 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
813 .addImm(Reg0)
821 Register Reg0 = MBBI->getOperand(0).getReg();
823 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR)
829 .addImm(RegInfo->getSEHRegNum(Reg0))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
AMDGPUBaseInfo.h 749 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
AMDGPUBaseInfo.cpp 1473 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
1474 for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 1169 Register Reg0 = MI.getOperand(0).getReg();
1179 if (Reg0 == Reg1) {
1199 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
1202 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))

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