| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 636 unsigned Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true);
651 Reg2 = getXRegFromWReg(Reg2);
653 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
656 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
659 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
662 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
665 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
670 Reg2 = getDRegFromBReg(Reg2);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.h | 94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
|
| MipsAsmPrinter.cpp | 876 unsigned Reg2) {
885 Reg1 = Reg2;
886 Reg2 = Temp;
890 I.addOperand(MCOperand::createReg(Reg2));
896 unsigned Reg2, unsigned Reg3) {
900 I.addOperand(MCOperand::createReg(Reg2));
907 unsigned Reg2, unsigned FPReg1,
911 Reg1 = Reg2;
912 Reg2 = temp;
915 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2)
[all...] |
| Mips16InstrInfo.h | 120 unsigned Reg1, unsigned Reg2) const;
|
| MicroMipsSizeReduction.cpp | 377 // Returns true if the registers Reg1 and Reg2 are consecutive
378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) {
388 if (Registers[i + 1] == Reg2)
407 Register Reg2 = MI2->getOperand(0).getReg();
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2)));
479 Register Reg2 = MI2->getOperand(1).getReg();
481 if (Reg1 != Reg2)
|
| Mips16InstrInfo.cpp | 278 unsigned Reg1, unsigned Reg2) const {
282 // move reg2, sp
283 // add reg1, reg1, reg2
289 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
293 MIB3.addReg(Reg2, RegState::Kill);
|
| MipsTargetStreamer.h | 134 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
136 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 2165 static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2,
2174 if (Reg2 == AArch64::FP)
2178 if (Reg2 == Reg1 + 1)
2186 (Reg1 - AArch64::X19) % 2 == 0 && Reg2 == AArch64::LR && !IsFirst)
2191 /// Returns true if Reg1 and Reg2 cannot be paired using a ldp/stp instruction.
2195 static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2,
2199 return invalidateWindowsRegisterPairing(Reg1, Reg2, NeedsWinCFI, IsFirst);
2204 return Reg2 == AArch64::LR;
2213 unsigned Reg2 = AArch64::NoRegister;
2220 bool isPaired() const { return Reg2 != AArch64::NoRegister;
[all...] |
| AArch64LowerHomogeneousPrologEpilog.cpp | 198 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2,
201 assert(!(IsFloat ^ AArch64::FPR64RegClass.contains(Reg2)));
211 MIB.addReg(Reg2)
221 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2,
224 assert(!(IsFloat ^ AArch64::FPR64RegClass.contains(Reg2)));
234 MIB.addReg(Reg2, getDefRegState(true))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 418 Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
988 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
990 bool &HaveReg2, Register &Reg2,
1017 // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
1065 if (parseIntegerRegister(Reg2, RegGR))
1068 if (isParsingATT() && parseRegister(Reg2))
1101 Register Reg1, Reg2;
1108 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1127 // There must be no Reg2.
1145 // If we have Reg2, it must be an address register
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCVSXFMAMutate.cpp | 190 Register Reg2 = MI.getOperand(2).getReg();
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill()
193 && Reg2 != OldFMAReg) {
|
| PPCVSXSwapRemoval.cpp | 897 Register Reg2 = MI->getOperand(2).getReg();
898 MI->getOperand(1).setReg(Reg2);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.h | 103 // Union Reg1's and Reg2's groups to form a new group.
105 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
|
| TargetInstrInfo.cpp | 186 Register Reg2 = MI.getOperand(Idx2).getReg();
201 bool Reg2IsRenamable = Register::isPhysicalRegister(Reg2)
209 Reg0 = Reg2;
211 } else if (HasDef && Reg0 == Reg2 &&
232 CommutedMI->getOperand(Idx1).setReg(Reg2);
245 if (Register::isPhysicalRegister(Reg2))
|
| AggressiveAntiDepBreaker.cpp | 89 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) {
95 unsigned Group2 = GetGroup(Reg2);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 166 unsigned Reg2, bool isKill2) {
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 760 Register Reg2 = MI->getOperand(2).getReg();
763 || !isARMLowRegister(Reg2))
765 if (Reg0 != Reg2) {
795 Register Reg2 = MI->getOperand(2).getReg();
796 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
|
| A15SDOptimizer.cpp | 83 unsigned Reg2);
448 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) {
456 .addReg(Reg2)
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetRegisterInfo.h | 100 bool contains(Register Reg1, Register Reg2) const {
103 if (!Reg1.isPhysical() || !Reg2.isPhysical())
105 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg());
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 78 bool contains(MCRegister Reg1, MCRegister Reg2) const {
79 return contains(Reg1) && contains(Reg2);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsTargetStreamer.cpp | 221 unsigned Reg2, SMLoc IDLoc,
223 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
227 unsigned Reg2, MCOperand Op3, SMLoc IDLoc,
233 TmpInst.addOperand(MCOperand::createReg(Reg2));
|
| /src/external/apache2/llvm/dist/llvm/lib/MC/ |
| MCDwarf.cpp | 1348 unsigned Reg2 = Instr.getRegister2();
1351 Reg2 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg2);
1355 Streamer.emitULEB128IntValue(Reg2);
|
| /src/games/warp/ |
| config.h.SH | 214 * This symbol, along with Reg2, Reg3, etc. is either the word "register"
223 #define $reg2 /**/
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | 1761 StringRef Reg2(R2);
1765 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1905 StringRef Reg2(R2);
1909 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 1396 CodeGenRegister *Reg2 = I1.second;
1398 if (&Reg1 == Reg2)
1400 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
1406 if (Reg2 == Reg3)
|
