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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
RegisterBank.h 92 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
93 RegBank.print(OS);
RegisterBankInfo.h 60 const RegisterBank *RegBank;
66 const RegisterBank &RegBank)
67 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {}
79 /// Check that the Mask is compatible with the RegBank.
80 /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
464 const RegisterBank &RegBank) const;
472 const RegisterBank &RegBank) const;
596 /// \note The mapping RC -> RegBank could be built while adding the
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
RegisterInfoEmitter.cpp 62 CodeGenRegBank &RegBank = Target.getRegBank();
63 RegBank.computeDerivedInfo();
91 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
93 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
95 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
208 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
210 unsigned NumRCs = RegBank.getRegClasses().size();
211 unsigned NumSets = RegBank.getNumRegPressureSets();
217 for (const auto &RC : RegBank.getRegClasses()) {
219 OS << " {" << RC.getWeight(RegBank) << ", ";
    [all...]
CodeGenRegisters.cpp 76 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
85 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]);
86 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]);
100 IdxParts.push_back(RegBank.getSubRegIdx(Part));
165 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
174 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i]));
175 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i]));
190 CodeGenRegister *Reg = RegBank.getReg(Alias);
252 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
264 CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
    [all...]
CodeGenTarget.h 53 mutable std::unique_ptr<CodeGenRegBank> RegBank;
110 /// Return the largest register class on \p RegBank which supports \p Ty and
113 getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
CodeGenRegisters.h 201 // This is valid after computeSubRegs visits all registers during RegBank
216 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
251 bool inheritRegUnits(CodeGenRegBank &RegBank);
258 unsigned getWeight(const CodeGenRegBank &RegBank) const;
397 getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank,
448 void buildRegUnitSet(const CodeGenRegBank &RegBank,
CodeGenTarget.cpp 282 auto &RegClasses = RegBank->getRegClasses();
336 if (!RegBank)
337 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes());
338 return *RegBank;
343 CodeGenRegBank &RegBank,
347 auto &RegClasses = RegBank.getRegClasses();
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
RegisterBankInfo.cpp 72 const RegisterBank &RegBank = getRegBank(Idx);
73 assert(Idx == RegBank.getID() &&
75 LLVM_DEBUG(dbgs() << "Verify " << RegBank << '\n');
76 assert(RegBank.verify(TRI) && "RegBank is invalid");
125 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg));
127 assert(RegBank.covers(*RC) &&
129 return &RegBank;
268 const RegisterBank *RegBank) {
269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0)
    [all...]
RegBankSelect.cpp 122 const RegisterBank *DesiredRegBank = ValMapping.BreakDown[0].RegBank;
263 const RegisterBank *DesiredRegBank = ValMapping.BreakDown[0].RegBank;
604 MRI->setRegBank(Reg, *ValMapping.BreakDown[0].RegBank);
  /src/external/gpl3/gdb.old/dist/sim/rl78/
cpu.c 54 } RegBank;
59 static RegBank *regbase_table[256];
83 regbase_table[i] = (RegBank *)(memory + (3 - rb) * 8 + REGISTER_ADDRESS);
  /src/external/gpl3/gdb/dist/sim/rl78/
cpu.c 54 } RegBank;
59 static RegBank *regbase_table[256];
83 regbase_table[i] = (RegBank *)(memory + (3 - rb) * 8 + REGISTER_ADDRESS);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 138 unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI);
190 assert(RegBank && "Can't get reg bank for virtual register");
193 assert((RegBank->getID() == ARM::GPRRegBankID ||
194 RegBank->getID() == ARM::FPRRegBankID) &&
197 if (RegBank->getID() == ARM::FPRRegBankID) {
356 unsigned RegBank,
360 if (RegBank == ARM::GPRRegBankID) {
374 if (RegBank == ARM::FPRRegBankID) {
1087 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID()
    [all...]
ARMRegisterBankInfo.cpp 52 PM.RegBank->getID() == RegBankID;
479 (Mapping.RegBank->getID() != ARM::FPRRegBankID ||
  /src/external/gpl3/gdb.old/dist/sim/arm/
armsupp.c 44 return (state->RegBank[ModeToBank ((ARMword) mode)][reg]);
56 state->RegBank[ModeToBank ((ARMword) mode)][reg] = value;
288 changes. The regbank matrix is largely unused, only rows 13 and 14 are
316 state->RegBank[USERBANK][i] = state->Reg[i];
317 state->RegBank[oldbank][13] = state->Reg[13];
318 state->RegBank[oldbank][14] = state->Reg[14];
322 state->RegBank[FIQBANK][i] = state->Reg[i];
326 state->RegBank[DUMMYBANK][i] = 0;
342 state->Reg[i] = state->RegBank[USERBANK][i];
343 state->Reg[13] = state->RegBank[newbank][13]
    [all...]
armos.c 717 ARMword addr = state->RegBank[UNDEFBANK][14] - 4;
857 state->RegBank[SVCBANK][14] = state->Reg[14] = state->Reg[15] - i_size;
arminit.c 93 state->RegBank[j][i] = 0;
armdefs.h 79 ARMword RegBank[7][16]; /* all the registers */
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPURegisterBankInfo.cpp 39 /// type of boolean operations to be regbank legal. All SALU booleans need to be
189 // registers we need to set the regbank on also referenced in a new
264 ValMapping.BreakDown[0].RegBank == ValMapping.BreakDown[1].RegBank);
1148 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
1425 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
1427 OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
1548 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
1877 const RegisterBank &RegBank,
1889 B.getMRI()->setRegBank(ShiftAmt.getReg(0), RegBank);
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/MIRParser/
MIParser.h 37 UNKNOWN, NORMAL, GENERIC, REGBANK
42 const RegisterBank *RegBank;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/
MIRParser.cpp 562 Info.D.RegBank = nullptr;
569 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value);
570 if (!RegBank)
575 Info.Kind = VRegInfo::REGBANK;
576 Info.D.RegBank = RegBank;
644 case VRegInfo::REGBANK:
645 MRI.setRegBank(Reg, *Info.D.RegBank);
MIParser.cpp 298 const auto &RegBank = RBI->getRegBank(I);
300 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank));
1351 case VRegInfo::REGBANK:
1358 const RegisterBank *RegBank = nullptr;
1360 RegBank = PFS.Target.getRegBank(Name);
1361 if (!RegBank)
1370 case VRegInfo::REGBANK:
1371 RegInfo.Kind = RegBank ? VRegInfo::REGBANK : VRegInfo::GENERIC
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineRegisterInfo.cpp 64 const RegisterBank &RegBank) {
65 VRegInfo[Reg].first = &RegBank;
MachineVerifier.cpp 1947 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
1950 if (!RegBank && isFunctionRegBankSelected) {
1958 if (RegBank && Ty.isValid() &&
1959 RegBank->getSize() < Ty.getSizeInBits()) {
1962 errs() << "Register bank " << RegBank->getName() << " too small("
1963 << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstructionSelector.cpp 194 llvm_unreachable("Unknown RegBank!");
200 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI);
201 return getRegClass(Ty, RegBank);
1323 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1327 MRI.setRegBank(DefReg, RegBank);
1333 MRI.setRegBank(Tmp, RegBank);
1392 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1397 getLoadStoreOp(DstTy, RegBank, TargetOpcode::G_LOAD, Alignment);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64RegisterBankInfo.cpp 630 assert(DstRB && SrcRB && "Both RegBank were nullptr");
738 *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[0]].RegBank,
739 *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[1]].RegBank,

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