HomeSort by: relevance | last modified time | path
    Searched refs:RegClassInfo (Results 1 - 25 of 31) sorted by relevancy

1 2

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
AllocationOrder.cpp 30 const RegisterClassInfo &RegClassInfo,
34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
CriticalAntiDepBreaker.h 41 const RegisterClassInfo &RegClassInfo;
RegAllocBase.h 69 RegisterClassInfo RegClassInfo;
RegAllocBase.cpp 65 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
128 ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC);
AllocationOrder.h 83 /// @param RegClassInfo Information about reserved and allocatable registers.
85 const RegisterClassInfo &RegClassInfo,
BreakFalseDeps.cpp 38 RegisterClassInfo RegClassInfo;
153 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
286 RegClassInfo.runOnMachineFunction(mf);
AggressiveAntiDepBreaker.h 122 const RegisterClassInfo &RegClassInfo;
RegAllocFast.cpp 79 RegisterClassInfo RegClassInfo;
777 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
830 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
961 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
1195 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size();
1196 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size();
1523 RegClassInfo.runOnMachineFunction(MF);
MachineCombiner.cpp 76 RegisterClassInfo RegClassInfo;
561 TII->shouldReduceRegisterPressure(MBB, &RegClassInfo);
722 RegClassInfo.runOnMachineFunction(MF);
PostRASchedulerList.cpp 80 RegisterClassInfo RegClassInfo;
289 RegClassInfo.runOnMachineFunction(Fn);
312 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode,
RegAllocGreedy.cpp 855 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix);
967 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg())) <
968 RegClassInfo.getNumAllocatableRegs(
1139 MCRegister CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg);
1171 uint8_t MinCost = RegClassInfo.getMinCost(RC);
1181 OrderLimit = RegClassInfo.getLastCostChange(RC);
1198 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI)
1710 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
2031 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
2097 if (!RegClassInfo.isProperSubClass(CurRC)
    [all...]
RegAllocBasic.cpp 268 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix);
CriticalAntiDepBreaker.cpp 45 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
402 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
MachineSink.cpp 124 RegisterClassInfo RegClassInfo;
430 RegClassInfo.runOnMachineFunction(MF);
714 RPTracker.init(MBB.getParent(), &RegClassInfo, nullptr, &MBB, MBB.end(),
MachineScheduler.cpp 155 RegClassInfo = new RegisterClassInfo();
159 delete RegClassInfo;
404 RegClassInfo->runOnMachineFunction(*MF);
1018 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin,
1020 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
1072 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
1102 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID);
1285 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
2943 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
AggressiveAntiDepBreaker.cpp 125 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) {
624 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
TargetRegisterInfo.cpp 57 const RegClassInfo *const RCIs,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIPreAllocateWWMRegs.cpp 38 RegisterClassInfo RegClassInfo;
103 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) {
211 RegClassInfo.runOnMachineFunction(MF);
GCNSchedStrategy.cpp 39 SGPRExcessLimit = Context->RegClassInfo
41 VGPRExcessLimit = Context->RegClassInfo
SIMachineScheduler.h 446 RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineScheduler.h 128 RegisterClassInfo *RegClassInfo;
387 RegisterClassInfo *RegClassInfo;
431 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure),
TargetRegisterInfo.h 235 struct RegClassInfo {
247 const RegClassInfo *const RCInfos;
257 const RegClassInfo *const RCIs,
719 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const {
MachinePipeliner.h 68 RegisterClassInfo RegClassInfo;
116 const RegisterClassInfo &RegClassInfo;
197 RegClassInfo(rci), II_setByPragma(II), Topo(SUnits, &ExitSU) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonMachineScheduler.h 99 RegisterClassInfo *getRegClassInfo() { return RegClassInfo; }
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.h 367 RegisterClassInfo *RegClassInfo) const override;

Completed in 58 milliseconds

1 2