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    Searched refs:RegEnc (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp 920 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
921 VEX_R = ~(RegEnc >> 3) & 1;
922 EVEX_R2 = ~(RegEnc >> 4) & 1;
935 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
936 VEX_R = ~(RegEnc >> 3) & 1;
937 EVEX_R2 = ~(RegEnc >> 4) & 1;
961 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
962 VEX_R = ~(RegEnc >> 3) & 1;
975 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
976 VEX_R = ~(RegEnc >> 3) & 1
    [all...]
X86AsmBackend.cpp 1331 uint32_t RegEnc = 0;
1341 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
1344 assert((RegEnc & 0x3FFFF) == RegEnc &&
1346 return RegEnc;
1550 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
1551 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
1555 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
1588 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
1589 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
SIMCCodeEmitter.cpp 407 uint64_t RegEnc = 0;
413 RegEnc |= MRI.getEncodingValue(Reg);
414 RegEnc &= SDWA9EncValues::SRC_VGPR_MASK;
416 RegEnc |= SDWA9EncValues::SRC_SGPR_MASK;
418 return RegEnc;
437 uint64_t RegEnc = 0;
443 RegEnc |= MRI.getEncodingValue(Reg);
444 RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
445 RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK;
447 return RegEnc;
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