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    Searched refs:RegID (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
RegisterFile.cpp 109 MCPhysReg RegID = WS.getRegisterID();
110 assert(RegID != 0 && "A write of an invalid register?");
115 MCPhysReg RenameAs = RegisterMappings[RegID].second.RenameAs;
116 if (RenameAs && RenameAs != RegID)
117 RegID = RenameAs;
119 WriteRef &WR = RegisterMappings[RegID].first;
123 for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {
132 for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) {
224 MCPhysReg RegID = WS.getRegisterID();
225 assert(RegID && "Adding an invalid register definition?")
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/MCA/
Instruction.cpp 21 void WriteState::writeStartEvent(unsigned IID, MCPhysReg RegID,
24 CRD.RegID = RegID;
30 void ReadState::writeStartEvent(unsigned IID, MCPhysReg RegID,
43 CRD.RegID = RegID;
126 dbgs() << "{ OpIdx=" << WD->OpIndex << ", Lat=" << getLatency() << ", RegID "
InstrBuilder.cpp 636 MCPhysReg RegID = 0;
644 RegID = Op.getReg();
647 RegID = RD.RegisterID;
651 if (!RegID)
655 NewIS->getUses().emplace_back(RD, RegID);
695 RegID = WD.isImplicitWrite() ? WD.RegisterID
698 if (WD.IsOptionalDef && !RegID) {
703 assert(RegID && "Expected a valid register ID!");
704 NewIS->getDefs().emplace_back(WD, RegID,
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
Instruction.h 57 // Optional definitions are allowed to reference regID zero (i.e. "no
86 /// Field RegID is set to the invalid register for memory dependencies.
89 MCPhysReg RegID;
150 WriteState(const WriteDescriptor &Desc, MCPhysReg RegID,
152 : WD(&Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(RegID), PRFID(0),
204 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
257 ReadState(const ReadDescriptor &Desc, MCPhysReg RegID)
258 : RD(&Desc), RegisterID(RegID), PRFID(0), DependentWrites(0),
276 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
  /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/
BottleneckAnalysis.h 252 void addRegisterDep(unsigned From, unsigned To, unsigned RegID,
254 addDependency(From, To, {DependencyEdge::DT_REGISTER, RegID, Cost});
314 void addRegisterDep(unsigned From, unsigned To, unsigned RegID, unsigned Cy);
BottleneckAnalysis.cpp 454 unsigned RegID, unsigned Cost) {
458 DG.addRegisterDep(From, To + SourceSize, RegID, Cost);
459 DG.addRegisterDep(From + SourceSize, To + (SourceSize * 2), RegID, Cost);
462 DG.addRegisterDep(From + SourceSize, To + SourceSize, RegID, Cost);
523 addRegisterDep(From, To, RegDep.RegID, Cycles);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86MCTargetDesc.cpp 432 auto ClearsSuperReg = [=](unsigned RegID) {
437 if (GR32RC.contains(RegID))
448 return VR128XRC.contains(RegID) || VR256XRC.contains(RegID);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 6417 auto RegID = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr ?
6419 return getPreloadedValue(DAG, *MFI, VT, RegID);

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